Method for forming gate oxide with uniform thickness

Abstract

The invention discloses a method for forming a gate oxide with uniform thickness, comprising the following steps of: 1. etching a groove on a silicon chip; 2. depositing filling silicon oxide into the groove fully; 3. flattening the filling silicon oxide by a chemical and mechanical polishing technology until silicon nitride is exposed; 4. etching the filling silicon oxide above the groove by a wet method, wherein the etched filling silicon oxide is still higher than an active area of the silicon chip; 5. etching the silicon nitride at both sides of the groove by the wet method until isolating silicon nitride is exposed; 6. carrying out pre-decrystallizing ion implantation of silicon ions for the silicon chip to form an amorphous layer in the active area below the etched silicon nitride; 7. etching the silicon nitride and the isolating silicon nitride on the surface of the silicon chip by the wet method; and 8. growing the gate oxide on the surface of the silicon chip. The method improves the thickness uniformity of the gate oxide through the pre-decrystallizing ion implantation before the growth of the gate oxide.

Description

technical field [0001] The invention relates to an integrated circuit manufacturing process, in particular to a method for manufacturing a gate oxide layer. Background technique [0002] Shallow trench isolation (STI) technology is a commonly used isolation process in sub-0.25μm devices. Its advantages are small occupied area, uniform thickness of filled oxide, and good isolation effect. [0003] Before performing the shallow trench isolation process, the active area has been defined on the silicon wafer. The shallow trench isolation process usually includes the following steps: [0004] Step 1, see Figure 1a . A layer of isolation silicon oxide 11 is grown on the surface of the silicon wafer 10 first. A layer of silicon nitride 12 is then deposited on the surface of the silicon wafer 10 . Next, the photoresist 13 is coated on the surface of the silicon wafer 10 to form an etching window 131 after exposure and development. Next, silicon nitride 12 , silicon oxide 11 an...

AI Technical Summary

Problems solved by technology

The uneven gate oxide layer leads to uneven threshold voltage of the transistor, so a hump phenomenon appears in the relationship between the leakage current and the gate voltage of the device, which makes the sub-threshold characteristics of the transistor worse and the leakage current increases significantly

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