Chip scale package structure of CMOS (complementary metal-oxide-semiconductor) image sensor and packaging method

Abstract

The invention discloses a chip scale package structure of a CMOS (complementary metal-oxide-semiconductor) image sensor and a packaging method. The chip scale package structure of the CMOS image sensor comprises a wiring layer, a photoelectric conversion layer, a pixel element array, a connection layer, a photic zone, an adhesion layer, a supporting layer, a conductive plug adapter, a bonding pad and solder joints, wherein the wiring layer equipped with a split connection pad; the photoelectric conversion layer is positioned on the surface of the wiring layer, and the photoelectric conversion layer and the connection pad are positioned at an opposite surface of the wiring layer; the pixel element array is positioned on the photoelectric conversion layer; the connection layer is positioned on the photoelectric conversion layer for separating the pixel element array and is higher than a pixel element; the photic zone is positioned on the connection layer and covers the pixel element, a cavity is formed on a pixel element area, and the adhesion layer is positioned on the wiring layer and covers the connection pad; the supporting layer is positioned on the adhesion layer; the conduction plug adapter penetrates through the supporting layer and the adhesion layer and expose the connection pad; and the bonding pad is positioned on the conductive plug adapter, and the solder spots are positioned on the surface of the bonding pad. The invention effectively improves the performance and the integration level of a device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip-level packaging structure and packaging method of a CMOS image sensor. Background technique [0002] At present, the charge coupled device (CCD) is the main practical solid-state image sensing device, which has the advantages of low read noise, large dynamic range, and high response sensitivity. The disadvantage of Complementary-Metal-Oxide-Semiconductor (CMOS) technology compatibility is that it is difficult to achieve single-chip integration with CCD-based image sensors. [0003] The CMOS image sensor (CMOS Image sensor, CIS) is produced in order to overcome the complex manufacturing process and high energy consumption of the charge-coupled device (CCD). MOS transistors. Due to the use of CMOS technology, CIS can integrate the pixel unit array and peripheral circuits on the same chip. Compared with CCD, CIS has the advantages of small size, light weight, low pow...

AI Technical Summary

Problems solved by technology

For high-pixel CMOS sensors, the number of connection lines is huge, and the use of solder technology not only affects the freedom of the entire connection line layout, but also makes it difficult to reduce the package area, which cannot meet the requirements of device integration and miniaturization

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