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One-time programmable memory and manufacture and programming reading method

A manufacturing method and a one-time technology, applied in the direction of read-only memory, static memory, semiconductor/solid-state device manufacturing, etc., can solve the problems of reduced integration, large storage unit area, and increased manufacturing cost, and achieve increased integration and reduced Effect of small area and improved reliability

Active Publication Date: 2013-02-06
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The one-time programmable memory of this structure requires the gate transistor to have high withstand voltage performance due to the high programming voltage, but due to the relatively large area of ​​the thick gate oxide layer transistor, the area of ​​each memory cell is also relatively large. large, therefore, resulting in an increase in manufacturing cost and a decrease in integration

Method used

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  • One-time programmable memory and manufacture and programming reading method
  • One-time programmable memory and manufacture and programming reading method
  • One-time programmable memory and manufacture and programming reading method

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Experimental program
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Embodiment 1

[0076] figure 1 It is a side view of the one-time programmable memory cell structure of the n-type semi-transistor structure in the first embodiment of the present invention, figure 1 Including: polysilicon layer 101, thin gate oxide layer 102, p-type ion implantation region 103, n-type heavily doped region 104, shallow isolation trench 105, n-type well 106 and p-type substrate 107. The polysilicon layer 101 is connected to the thin gate oxide layer 102, and the thin gate oxide layer 102 is connected to the p-type ion implantation region 103. The p-type ion implantation region 103 is located in the n-type well 106, and the heavily doped region 104 is located in the p-type ion implantation region. In the region 103 , the polysilicon layer 101 is connected to the word line (WL, Word Line), and the n-type heavily doped region 104 is connected to the bit line (BL, Bit Line). The thin gate oxide layer 102 is connected to the p-type ion implantation region 103 . A predetermined di...

Embodiment 2

[0096] image 3 It is a side view of the one-time programmable memory cell structure of the p-type semi-transistor structure in the second embodiment of the present invention, image 3 Including: polysilicon layer 301, thin gate oxide layer 302, n-type ion implantation region 303, p-type heavily doped region 304, shallow isolation trench 305, p-type well 306 and p-type substrate 307. The polysilicon layer 301 is connected to the thin gate oxide layer 302, and the thin gate oxide layer 302 is connected to the n-type ion implantation region 303. The n-type ion implantation region 303 is located in the p-type well 306, and the p-type heavily doped region 304 is located in the n-type well. Ions are implanted into the region 303 . The polysilicon layer 301 is connected to the word line WL, and the p-type heavily doped region 304 is connected to the bit line BL. The thin gate oxide layer 302 is connected to the n-type ion implantation region 303 . A predetermined distance is main...

Embodiment 3

[0116] Figure 5 It is a side view of the one-time programmable memory cell structure of the n-type semi-transistor structure in the third embodiment of the present invention, Figure 5 Including: polysilicon layer 501, thin gate oxide layer 502, p-type lightly doped drain region 503, n-type heavily doped region 504, p-type ion implantation region 505, shallow isolation trench 506, n-type well 507 and p-type well Substrate 508 . The polysilicon layer 501 is connected to the thin gate oxide layer 502, the thin gate oxide layer 502 is adjacent to the p-type lightly doped drain region 503, the p-type lightly doped drain region 503, and the n-type heavily doped region 504 are located in the p-type ion implantation region In 505 , the p-type ion implantation region 505 is located in the n-type well 507 . The polysilicon layer 501 is connected to a word line (WL, WordLine), and the n-type heavily doped region 504 is connected to a bit line (BL, Bit Line). The thin gate oxide laye...

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Abstract

The invention discloses a one-time programmable memory and a manufacture and programming reading method of a semitransistor structure. A semitransistor comprises a programmable capacitor formed by a polysilicon layer, a gate oxide layer and an ion implantation zone, and a diode formed by the ion implantation zone and a heavily doped zone, wherein the programmable capacitor is connected with the diode in series, and the polysilicon layer is connected with a word line; and the heavily doped zone is connected with a bit line. By utilizing the characteristics that the programmable capacitor form an on resistance when being broken down and is still taken as an insulation capacitor when not being broken down, and the forward conducting and reverse-closing characteristic of the diode, the one-time programmable memory which has small memory cell area and high integration level, can further improve integration level with the development of process, is based on the existing logical process without adding a special process, and has high stability and reliability of data storage can be achieved.

Description

technical field [0001] The invention mainly relates to the field of semiconductor memory, in particular to a one-time programmable memory, a manufacturing method and a programming and reading method. Background technique [0002] At present, the design of the one-time programmable memory based on the logic technology mainly adopts the dynamic random access memory structure, and uses the breakdown characteristic of the gate oxide layer of the transistor to perform data programming. Each unit of this one-time programmable memory includes two transistors, one of which is a thick gate oxide transistor for input and output, which has high withstand voltage due to its thick gate oxide layer; the other A transistor is a thin gate oxide transistor used in the internal circuits of the chip, which is easily broken down at lower voltages due to its thin gate oxide. Since the thick gate oxide transistor has a gate characteristic, and the thin gate oxide transistor has a breakdown capac...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L21/8247G11C17/18H10B69/00
Inventor 朱一明苏如伟
Owner GIGADEVICE SEMICON (BEIJING) INC