High-spectrum image dimensionality reduction chip

A hyperspectral image and dimensionality reduction technology, applied in the field of image processing, can solve the problems of no real-time processing, no real-time dimensionality reduction processing of hyperspectral images, and achieve high module utilization efficiency, low research and development risk, and short development cycle. Effect

Inactive Publication Date: 2011-11-09
BEIJING INSTITUTE OF TECHNOLOGYGY
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Problems solved by technology

[0004] At present, Hongtao Du, Hairong Qi and GregoryD.Peterson of the University of Tennessee abroad proposed the idea of ​​using FPGA to achieve dimensionality reduction of hyperspectral images in the paper "Parallel ICA and its hardware implementation inhyperspectral image analysis", but they did not realize the function of real-time processing
Domestic hyperspectral image data dimensionality reduction technologies are all in the theoretical research stage, and no one uses FPGA for hardware to realize real-time dimensionality reduction processing of hyperspectral imagery

Method used

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  • High-spectrum image dimensionality reduction chip
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  • High-spectrum image dimensionality reduction chip

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Embodiment Construction

[0020] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0021] see figure 1 System-on-a-chip structure diagram. In this embodiment, the Vertix5 series experiment board of Xilinx Company is used to design, simulate and verify the dimensionality reduction chip. The whole chip system can be divided into five modules: system control module, autocorrelation module, eigenvalue solving module, eigenvalue extraction module, and dimension reduction realization module. Due to the massive amount of hyperspectral image data, there is not enough storage unit inside the FPGA to store the entire hyperspectral image, so an additional storage unit needs to be added externally, and a data input buffer needs to be added at the front end of the image transmission to make the hyperspectral image The image data is output to subsequent modules in the form of block matrix. The divided modules are independent of each oth...

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Abstract

The invention provides a high-spectrum image dimensionality reduction chip, which belongs to the field of image processing. The chip mainly completes the real-time dimensionality reduction processing on a large amount of high-spectrum image data. The chip is completed by adopting the VHDL speech, and is realized through being based on an in-site programmable gate array. The system chip manly comprises five parts: a system control module, a self correlation module, a feature value solving module, a feature value extracting module and a dimensionality reduction realization module. The inventioncan complete the real-time dimensionality reduction processing of the high-spectrum image data, and has the advantages of short development period, low design cost and low development risk.

Description

technical field [0001] The invention belongs to the field of image processing, and relates to a hyperspectral image dimensionality reduction chip and an implementation method. Background technique [0002] Hyperspectral images are ground object images acquired by hyperspectral imagers in hundreds of continuous narrow bands from visible light to near-infrared. Therefore, hyperspectral images have many bands, high spectral resolution, contain a lot of information, and have a huge amount of data. However, the problems it brings are high information redundancy, large space required for data storage, and long processing time. Therefore, it is very important to perform dimensionality reduction before processing and analyzing hyperspectral images. [0003] The real-time processing of massive hyperspectral images is a research hotspot at home and abroad. The main technical approach to solve the problem of real-time data processing of hyperspectral images is to reduce the dimensiona...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 谌德荣彭林科何光林
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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