Ultrathin film wet preparation method for TSV insulating layer

An ultra-thin film and insulating layer technology, applied in the field of microelectronic materials, can solve the problems of complex process, poor step coverage, high cost of insulating layer, and achieve the effect of simple process flow, low cost and good combination.

Inactive Publication Date: 2010-11-17
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to overcome the disadvantages of traditional sputtering methods such as high cost, complex process, and poor step coverage on the surface of through-silicon holes, as well as the difficulties of obtaining ultra-thin insulating layers in deep holes with general electrophoretic coating technology, and provide A kind of ultra-thin film wet preparation method for TSV insulating layer

Method used

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  • Ultrathin film wet preparation method for TSV insulating layer
  • Ultrathin film wet preparation method for TSV insulating layer
  • Ultrathin film wet preparation method for TSV insulating layer

Examples

Experimental program
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Effect test

Embodiment 1

[0031] Preparation of Ultrathin Insulating Film of Polyurethane Modified Epoxy Resin

[0032] This embodiment adopts cathodic electrophoretic coating process, and uses polyurethane modified epoxy resin electrophoretic coating, which specifically includes the following steps:

[0033] (1) Connect the silicon wafer to be processed to the conductive device, the conductive device is connected to the negative pole of the power supply, and the anode of the electrophoresis device is connected to the positive pole of the power supply as an anode system.

[0034] (2) Put the silicon wafer into the electrophoretic coating solution containing 10% polyurethane modified epoxy resin, under the condition of 25°C, apply ultrasonic oscillation with a frequency of 25KHZ, the rotational speed of the rotating electrode is 50rmp, and the electrophoretic voltage is set to 30V , cathodic electrophoresis 10S.

[0035] (3) After the electrophoretic coating is completed according to the required time,...

Embodiment 2

[0039] Preparation of Ultrathin Insulating Film of Modified Acrylic Polyurethane Resin

[0040] This embodiment adopts cathodic electrophoretic coating process, uses modified acrylic polyurethane resin coating, specifically comprises the following steps:

[0041] (1) Connect the silicon wafer to be processed to the conductive device, the conductive device is connected to the negative pole of the power supply, and the anode of the electrophoresis device is connected to the positive pole of the power supply as an anode system.

[0042] (2) Put the silicon wafer into the electrophoretic coating solution containing 20% ​​modified acrylic polyurethane resin, and under the condition of 25°C, apply ultrasonic oscillation with a frequency of 50KHZ, the rotational speed of the rotating electrode is 200rmp, and the electrophoretic voltage is set to 45V. Cathodic electrophoresis 30S.

[0043] (3) After the electrophoretic coating is completed according to the required time, the silicon ...

Embodiment 3

[0047] Preparation of Ultrathin Insulating Film of Acrylic Modified Epoxy Resin

[0048] This embodiment adopts the anodic electrophoretic coating process, and uses acrylic modified epoxy resin electrophoretic coating, which specifically includes the following steps:

[0049] (1) Connect the silicon wafer to be processed to the conductive device, the conductive device is connected to the positive pole of the power supply, and the cathode of the electrophoresis device is connected to the negative pole of the power supply as the cathode system.

[0050](2) Put the silicon wafer into the electrophoretic coating solution containing 30% acrylic modified epoxy resin, under the condition of 30°C, apply ultrasonic oscillation with a frequency of 68KHZ, the rotational speed of the rotating electrode is 300rmp, and the electrophoretic voltage is set to 60V , anodic electrophoresis 60S.

[0051] (3) After the electrophoretic coating is completed according to the required time, the silic...

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Abstract

The invention relates to an ultrathin film wet preparation method for a TSV insulating layer in the technical field of microelectronic materials, which comprises the following steps of: (1) connecting a silicon chip subjected to DRIE etching with a conductive device into an anode or cathode system serving as an anode or a cathode of the conductive device to connect an electrophoresis apparatus so as to form a circuit; (2) putting the silicon chip connected with the conductive device into electrophoretic coating solution; (3) switching on a power supply and starting to carry out electrophoretic coating; (4) after growth is completed, switching off the power supply, taking the silicon chip out of the electrophoretic coating solution and carrying out ultrasonic cleaning on a silicon through hole by using deionized water to wash off a suspended coating; and (5) carrying out primary drying and secondary drying treatment on the clean electrophoretic coated silicon chip. The ultrathin insulating film is prepared by the ultrafthin film wet preparation method of the invention. The thickness of the ultrathin insulating film is between 1 and 3mu m. The ultrathin insulating film has excellent bonding force. A test result shows that the breakdown voltage of the insulating film can reach over 2mV/cm. The process flow can be operated at a low temperature. The growth speed of the coating is high. The process cost is low.

Description

technical field [0001] The invention relates to a preparation method in the technical field of microelectronic materials, in particular to an ultra-thin film wet preparation method for TSV (ThroughSilicon Vias, through-silicon via) insulating layer. Background technique [0002] The development trend of the microelectronics industry is to improve performance and reduce cost. Traditional two-dimensional miniaturization strategies have reached the limits of performance, functional diversity, and manufacturing cost, and are gradually being replaced by three-dimensional semiconductor integration technologies. Among various 3D integration technologies, the stacked packaging method based on TSV vertical interconnection leads the development trend of 3D packaging technology with its key technical advantages of short-distance interconnection and high-density integration. TSV packaging includes a series of key technologies, silicon deep hole etching and forming, the formation of ins...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C25D13/06C25D13/12
Inventor 汪红李光杨丁桂甫姚锦元吴义伯杨春生
Owner SHANGHAI JIAO TONG UNIV
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