FPGA (Field Programmable Gate Array)-based bonded phase frequency doubling method and device
A key-phase and frequency multiplication technology, applied to logic circuits using basic logic circuit components, logic circuits using specific components, electrical components, etc., can solve the problem of multi-circuit area, inability to perform period prediction and error correction, and inability to adapt to distribution Miniaturization and other issues to achieve the effect of improving stability and reliability, reducing circuit consumption area, flexible and convenient modification
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- Publication Date
- 2010-12-15
Smart Images
Figure 1 Figure 2 Figure 3
Abstract
Description
technical field
[0001] The invention relates to the design of a Field Programmable Gates Array (Field Programmable Gates Array, FPGA), which is a method and a device for generating a key-phase frequency multiplication signal in the whole cycle sampling of the vibration signal of a rotating machine. Background technique
[0002] There are a large number of large-scale rotating machinery and equipment in the process of electric power, petrochemical, and metallurgy. They are the foundation of the national economy. Once such machinery fails, it may cause a chain reaction, causing the entire machinery or even the entire set of equipment to fail to work normally, resulting in huge economic losses. It can even cause serious catastrophic casualties. In order to manage and use this kind of major key equipment well, improve the stability, reliability, safety, service efficiency and life of this kind of machinery, and avoid causing major accidents and affecting social production, the c...
Examples
Embodiment Construction
[0025] Such as figure 1 As shown, the FPGA-based key phase frequency multiplier of this embodiment includes a square wave processor 1, an addition counter 2, a linear predictor 3, an error corrector 4, a divider 5, a key phase multiple register 6, a latch Device 7 and subtraction counter 8, described square wave processor 1, addition counter 2, linear predictor 3, error corrector 4, divider 5, key phase multiple register 6, latch 7 and subtraction counter 8 use hardware The description language VHDL is programmed and integrated into an FPGA. The key-phase frequency multiplier is a module in the FPGA device, which accepts the frequency f key The key phase square wave signal, the clock signal and the data in the FPGA configuration register, wherein the key phase multiple 2 is placed in the FPGA configuration register 9 k (k is a positive integer) data, the device output frequency is 2 k f key The frequency multiplied square wave signal; the output multiplied signal can be us...