Field effect transistor chiral sensor and manufacture method thereof
A field-effect transistor and sensor technology, applied in the field of sensors, can solve the problems of easy pollution and sensor application limitations, and achieve the effects of no reagent consumption, reduced environmental pollution, and easy deviceization
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Embodiment 1
[0026] What is obtained by this preparation method is a top-contact quantum dot field effect transistor chiral sensor:
[0027] Step 1, sputtering or evaporating a layer of gate electrode 2 with a thickness of 10nm-500nm on the substrate 1, the gate electrode is composed of one or two of Ta, Ti, Cr, W, Mo, Au or Ag.
[0028] Step 2, sputtering or evaporating a layer of high dielectric constant gate insulating layer 3 with a thickness of 150nm to 500nm, the gate insulating layer is made of SiO 2 、 Ta 2 o 5 、Al 2 o 3 、TiO 2 , BZT, or PZT in one or two forms.
[0029] Step 3, by spin coating, inkjet printing or screen printing a layer of active layer 4 with a thickness of 10 nm to 500 nm, wherein the active layer 4 can be one or both of the following two different compounds modified by chiral molecules Combination. They are: (a) Group II-VI compounds; (b) Group III-V compounds.
[0030] Step 4, sputtering, inkjet printing or evaporating a layer of source electrode 5 and d...
Embodiment 2
[0032] What is obtained by this preparation method is a bottom-contact quantum dot field effect transistor chiral sensor:
[0033] Step 1, sputtering or evaporating a layer of gate electrode 2 with a thickness of 10nm-500nm on the substrate 1, the gate electrode is composed of one or two of Ta, Ti, Cr, W, Mo, Au or Ag.
[0034] Step 2, sputtering or evaporating a layer of high dielectric constant gate insulating layer 3 with a thickness of 150nm to 500nm, the gate insulating layer is made of SiO 2 、 Ta 2 o 5 、Al 2 o 3 、TiO 2 , BZT, or PZT in one or two forms.
[0035] Step 3, sputtering, inkjet printing or evaporating a layer of source electrode 5 and drain electrode 6 composed of one or two of Au, Ag, Ti, PEDOT:PSS, etc. on the gate insulating layer 3 .
[0036] Step 4, on the gate insulating layer 3 and the source / drain electrodes, a layer of active layer 4 with a thickness of 10 nm to 500 nm is printed by vacuum thermal evaporation, spin coating, inkjet printing or scre...
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