FPGA-based JTAG test method

Abstract

The invention relates to a field programmable gate array (FPGA)-based joint test action group (JTAG) test method. In the method, an FPGA is connected with a circuit board to be tested by a JTAG interface and a probe; when a test is performed through the JTAG interface, the probe led out of the FPGA is connected with a monitoring point of the circuit board to be tested so as to read the data change of each point during the test; and finally, the FPGA sends the data change to a personal computer (PC) or a microprocessor for data analysis and judgment through an asynchronous series-port circuit.By the FPGA-based JTAG test method, a welding defect of a ball grid array (BGA) chip and the welding condition of the circuit around the chip can be precisely judged.

Description

【Technical field】 [0001] The invention relates to the field of electronic technology, in particular to a JTAG test method implemented based on FPGA. 【Background technique】 [0002] In order to solve the testing problem of VLSI, the Joint Test Action Group (JTAG) proposed the boundary-scan technology, which tests the device and its peripheral circuits through the boundary-scan unit existing between the input and output pins of the device and the core circuit. , thereby improving the controllability and observability of the device, solving the above-mentioned test problems brought about by the development of modern electronic technology, and can more conveniently complete the test of the circuit board assembled by the modern device. Often this test is called a JTAG link test. [0003] There are many schemes for designing circuit board testing based on the JTAG standard IEEE1149, and its advantage is that online testing can be performed. Soldering defects of some components o...

AI Technical Summary

Problems solved by technology

[0006] 1. Only the specific pins of sluggish 0 or sluggish 1 can be tested, but it is impossible to determine where the sluggishness occurs, for example, it appears on the connection line with other chips, or it appears on the ball solder joint under the BGA. difficult to determine

[0007] 2. It is impossible to judge the open circuit, because the data of the JTAG chain itself is not affected by the pin signal when the circuit is open, so the open circuit cannot be judged

[0008] 3. Only the soldering point of the chip itself can be tested, because the characteristic of the JTAG chain is that it is embedded inside the chip, and whether there are soldering problems in other devices connected to it cannot be tested

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