DSP (Digital Signal Processing) chip-oriented instruction scheduling method

An instruction scheduling and chip technology, applied in the field of compilers, can solve problems such as being limited to a specific function, large amount of audio and video data, etc., to achieve the effect of improving efficiency and optimizing processing programs

Inactive Publication Date: 2011-05-18
SICHUAN JIUZHOU ELECTRIC GROUP
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AI Technical Summary

Problems solved by technology

However, the amount of audio and video data is large, and there are high requirements for the computing power of the chip. Therefore, in order to realize many high-end applications of audio and video technology, it is necessary to find ways to improve the processing power of the chip.
And the assembly code of the DSP chip in the prior art is generally limited to a certain specific function

Method used

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  • DSP (Digital Signal Processing) chip-oriented instruction scheduling method
  • DSP (Digital Signal Processing) chip-oriented instruction scheduling method
  • DSP (Digital Signal Processing) chip-oriented instruction scheduling method

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Embodiment Construction

[0017] The present invention will be further elaborated below in conjunction with the accompanying drawings.

[0018] First call the GCC (compiler for programming under the linux system) compiler to generate the assembly code file corresponding to the computer language code, and then based on the assembly file, perform the following series of instruction scheduling methods for DSP chips to generate the same name The assembly code file is finally handed over to the linker to generate an executable file.

[0019] Such as figure 1 A schematic diagram of the steps of the shown DSP chip-oriented instruction scheduling method, which includes the following steps:

[0020] Step A. constructing topological sorting between assembler basic block statements;

[0021] Step B. On the basis of the topological sort obtained in step A, calculate the delay value delay of each instruction in the assembly language program basic block;

[0022] Step C. Traversing the data dependency graph from ...

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Abstract

The invention relates to a DSP (Digital Signal Processing) chip oriented instruction scheduling method, which comprises the following steps of: step A. constructing topological sorting among basic block statements of an assembler; step B. calculating the delay of each instruction on the basis of the topological sorting obtained in the step A; step C. traversing a data dependence graph from root nodes to leaf nodes; and step D. finding out an instruction with the maximum delay in a candidate instruction set in the step C and executing time less than or equal to the current time and arranging the instruction in the current scheduling time slot. By means of modeling, the method realizes the optimization of a DSP chip which is not limited to a specific DSP chip on the market.

Description

technical field [0001] The present invention relates to compiler technology in computer science and technology, in particular to an instruction scheduling method for DSP (Digital Signal Processing: Digital Signal Processing, DSP for short) chips. Background technique [0002] With the continuous development of computer technology and multimedia technology, audio and video technology has become a mainstream direction in the field of computer science and technology research. However, the large amount of audio and video data has high requirements on the computing power of the chip. Therefore, in order to realize many high-end applications of audio and video technology, it is necessary to find ways to improve the processing power of the chip. However, the assembly code of the DSP chip in the prior art is generally limited to a certain specific function. Contents of the invention [0003] DSP chips in the prior art are generally limited to a specific function, so it is necessa...

Claims

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Application Information

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IPC IPC(8): G06F9/30
Inventor 汤睿范高生
Owner SICHUAN JIUZHOU ELECTRIC GROUP
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