Cell structure of one-time programmable memory (OTP) device and manufacturing method and operating method of cell structure
A technology of unit structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of unfavorable high-density integrated circuit application and large unit structure area, and achieve reliable data storage capacity, small area effect
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[0032] see figure 2 , the unit structure of the OTP device of the present invention is an NMOS, and a p-well 12 is formed on the substrate 10 . There is an isolation region 11 in the substrate 10 and / or the p-well 12, which is generally made of dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride and the like. On the p-well 12 there is a gate oxide layer 13 and silicon dioxide 16 , and the silicon dioxide 16 is on both sides of the gate oxide layer 13 . On the gate oxide layer 13 is a polysilicon gate 14 , on the silicon dioxide 16 there are silicon nitride sidewalls 17 , and the silicon nitride sidewalls 17 are on both sides of the polysilicon gate 14 . The polysilicon gate 14 only has an n-type lightly doped region 15 in the p-well 12 under one side. There are n-type heavily doped regions 18a and 18b in the p well 12 below the outer side of the silicon nitride spacer wall 17 . The surface of the silicon wafer is covered with a layer of silico...
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