Chemical vapor deposition method assisted by non-plasma

Abstract

The invention provides a chemical vapor deposition method assisted by non-plasma. The method comprises the following steps: cleaning sediment deposited on the inner wall of a reaction cavity before placing a wafer in the reaction cavity, depositing a layer of second sediment on the inner wall of the reaction cavity, and regulating the time of introducing protective gas according to the air pressure in the reaction cavity; and after placing the wafer in the reaction cavity, preparing a dielectric layer on the wafer by using the chemical vapor deposition method assisted by the non-plasma. By using the method, the sediment deposited on the inner wall of the reaction cavity is cleaned before placing the wafer in the reaction cavity so as to clean the sediment remained on the inner wall of the reaction cavity, then a layer of second sediment is deposited on the inner wall of the reaction cavity so that the environments in the reaction cavity are consistent with the environment when the wafer is placed in the reaction cavity to manufacture the dielectric layer; and through cleaning the reaction cavity and regulating the introduction time of the protective gas, the severe variation of the temperature in the reaction cavity is avoided so as to influence the thickness of the sequentially manufactured dielectric layer, and the variation range of the thickness of the dielectric layer is reduced.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a non-plasma assisted chemical vapor deposition method. Background technique [0002] In the semiconductor manufacturing process, several active devices are usually fabricated on the wafer, and the dielectric layer and the metal layer are fabricated layer by layer on the active device through the deposition process, through the dielectric layer, the through hole opened in the dielectric layer, through the The different metal layers connected by the holes connect the active devices fabricated on the wafer, which is the process of multi-layer metallization of the wafer. The interconnects formed on the metal layer are connected through the vias formed on the insulating layer to connect the active devices on the wafer. [0003] figure 1 It is a structural schematic diagram of multi-layer metallization on an existing wafer. Combine now figure 1 , the method of chemical vap...

AI Technical Summary

Problems solved by technology

Since the thickness of the dielectric layer produced on the non-plasma-assisted chemical vapor deposition reaction chamber wafer is different, and the resistance of the through hole is proportional to the thickness of the dielectric layer, this makes the error range of the contact resistance of the chip produced on the wafer Larger, affecting the quality of the chip

Images