Process for etching polycrystalline silicon layer and method for forming metal oxide semiconductor (MOS) transistor

Abstract

The invention relates to a process for etching a polycrystalline silicon layer and a method for forming a metal oxide semiconductor (MOS) transistor. The process for etching the polycrystalline silicon layer comprises the following steps of: providing a semiconductor substrate on which the polycrystalline silicon layer is formed; forming a first oxide layer on the polycrystalline silicon layer; etching the first oxide layer which at least comprises a device structure position, and forming an opening; forming barrier layers on the first oxide layer and the polycrystalline silicon layer; etching the barrier layers, and forming a side wall on the side wall of the first oxide layer, wherein the side wall is positioned in the opening and corresponds to the device structure position; removing the first oxide layer except the side wall position; etching the polycrystalline silicon layer by taking the side wall as a mask, and forming a device structure; and removing the side wall. By the process and the method, the high-precision polycrystalline silicon small line width etching is realized at low cost.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor devices, in particular to a process for etching a polysilicon layer and a method for forming a MOS transistor. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, integrated circuit chips are developing towards higher component density and high integration. Gate dimensions are getting thinner and shorter than ever. [0003] In the existing process of manufacturing MOS transistors, the gate is formed using a patterned photoresist layer as a mask, and the polysilicon layer on the gate dielectric layer is etched by a dry etching method to form the gate. specific process reference Figure 1 to Figure 2 ,like figure 1 As shown, a gate dielectric layer 102 is formed on a semiconductor substrate 100, and the method for forming t...

AI Technical Summary

Problems solved by technology

If the semiconductor device needs to achieve a smaller line width, there is generally no other way except to upgrade the hardware, such as purchasing a lithography machine with a stronger process capability

However, the price of purchasing a lithography machine is expensive, which increases the production cost

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