Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow

A technology of design data and design files, applied in computer-aided design, CAD circuit design, calculation, etc., can solve problems such as insufficient robustness or efficiency

Active Publication Date: 2015-03-25
OASIS TOOLING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

None of these approaches are robust or efficient enough

Method used

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  • Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow
  • Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow
  • Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0314] Example 1: Liberty formatted file

[0315] The Liberty library file format provides a way to describe the functionality and timing of a circuit to logic synthesis tools. It is defined by Synopsys and is widely used since Synopsys has published the specification. It is a text-based format that can be easily viewed, but due to the amount of data in a Liberty file, it is usually created by software.

[0316]In this first example, the generalization of Liberty design language files will be discussed. Some parts of the Liberty documentation are undocumented. "Undocumented" refers to normalized generalizations. In general, unit names are not generalized because doing so would prevent the matching of otherwise equivalent units with different names. Some parsers also skip required tokens and do not provide additional information such as fixed-position keywords or layer names (since digests are separated by layers anyway).

[0317] In some formats, the "text" that is reco...

example 2

[0436] Example 2: Verilog file type

[0437] Verilog is a simulation and register transfer logic (RTL) language widely used in integrated circuit design. It is a text-based format typically created by a designer and compiled by a logic synthesis tool. It allows designers to specify designs as interconnected blocks. Circuit functions are specified in blocks recorded as cells, and input and output ports are recorded as cell interfaces. Put hints to logic synthesis tools in attributes associated with module headers or statements.

[0438] In this example, the Verilog file has a content outline for the following file elements:

[0439] ●Documents

[0440] ●File header

[0441] ●Unit module port definition

[0442] ●The main body of the unit module

[0443] The file is scanned for internal module names. Separate digests are computed for the port definition and the body of the module. These are based on individual Verilog tokens excluding any white space.

[0444] Digest...

example 3

[0510] Example 3: Structured binary file type

[0511] In this example, structured binary file types that do not have a custom parser are treated as unstructured binary files.

[0512] Typically, all bytes are assigned a digest without knowing the structure of the binary. In order to assign a digest to specific content within a structured binary, the data structure needs to be known, and a parser written for it needs to be.

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Abstract

The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header / cell portions, by separate handling of comments, by functionally significant / non-significant data, by whitespace / non-whitespace, and by layer within a unit of design data. The similarities and differences of interest depend on the purpose of the granular analysis. The comparisons are useful in many ways.

Description

[0001] related application [0002] This application claims the benefit of filed US Patent Provisional Application No. 61 / 131,601 and US Patent Provisional Application No. 61 / 180,715. Prior applications incorporated by reference. Background technique [0003] The disclosed techniques relate to granular analysis of design data used to prepare a chip design for fabrication, and to identifying similarities and differences between portions of the design data file. In particular, the disclosed techniques relate to parsing and organizing data into a normalized form, summarizing the normalized form, and comparing summaries of design data from different sources, such as chip-level designs and design template libraries. Organizing design data into a normalized form generally reduces the sensitivity of data analysis to data changes that have no functional impact on the design. The details of granular analysis vary with the design language used to represent aspects of the design, as w...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F17/5045G06F17/5081G06F17/504G06F30/3323G06F30/398G06F30/30
Inventor D·查普曼T·格里宾斯基
Owner OASIS TOOLING
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