Method for manufacturing SOI (silicon on insulator) super junction LDMOS (lateral double-diffused metal oxide semiconductor) device with buffer layer

Abstract

The invention discloses a method for manufacturing an SOI (silicon on insulator) super junction LDMOS (lateral double-diffused metal oxide semiconductor) device with a buffer layer. The method comprises the following steps: firstly implanting N-type ions into top silicon of an SOI substrate to ensure the region below a whole drift region to become an N-type region; secondly implanting shallowly doped N-type ions into the drift region and forming a shallowly doped N-type buffer layer on the surface layer of the drift region; and thirdly implanting P-type ions into the formed N-type region via a layout and forming a plurality of equally spaced lateral P-type column regions in the N-type region to divide the N-type region into a plurality of lateral N-type column regions, wherein the alternately arranged P-type column regions and N-type column regions form a lateral super junction structure. The method has the following beneficial effects: the buffer layer is arranged on the drift region, thus inhibiting the impact of the substrate-assisted depletion effect on the balance of the charges in the SOI super junction LDMOS drift region and improving the breakdown voltage of the device; and by skillfully adjusting the step of implanting N / P ions and designing the layout and ion implantation concentration, the process is further simplified and the production cost is lowered.

Description

technical field [0001] The invention relates to a method for manufacturing a lateral double-diffused metal oxide semiconductor (LDMOS, LateralDouble-diffused MOSFET) device structure, especially a method for manufacturing an SOI superjunction LDMOS device with a buffer layer, which belongs to microelectronics and solid-state electronics technology field. Background technique [0002] Lateral Double-diffused MOSFET (LDMOS, Lateral Double-diffused MOSFET) is the key technology of high-voltage integrated circuit HVIC (High Voltage Integrated Circuit) and power integrated circuit PIC (Power Integrated Circuit). Its main feature is that a relatively long lightly doped drift region is added between the channel region and the drain region. The doping type of the drift region is consistent with that of the drain end. By adding the drift region, it can share the breakdown voltage. [0003] The so-called super-junction LDMOS is an improved LDMOS, that is, the low-doped N-type drift r...

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Problems solved by technology

[0006] However, if a design requires thick-film SOI (thickness t si >1.5um), the introduction of a buffer layer can alleviate the substrate-assisted depletion effect of SOI lateral superjunction devices, but since the buffer layer is located on the buried oxide layer below the drift region, it is necessary to achieve such an implantation depth during ion implantation , not only the implantation energy must be very large, but also the impurity distribution must be precisely controlled, and the process is very difficult to realize

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