CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit

Abstract

The invention provides a CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit which is used for protecting a functional unit. The CDM ESD protection circuit comprises a first stage of ESD protection unit, a low voltage trigger protection unit, a second stage of ESD protection unit and a local ESD protection unit, wherein the first end of the low voltage trigger protection unit is coupled to the input / output pin, and the second end of the low voltage trigger protection unit is coupled to the substrate. When the electric potential of the substrate is smaller than that of the input / output pin and exceeds a second specific voltage, the low voltage trigger protection unit operates. Therefore, the performance of the CDM ESD protection circuit is improved.

Description

technical field [0001] The invention relates to an electrostatic discharge (ESD) circuit, in particular to a CDM ESD protection circuit. Background technique [0002] Integrated circuits (ICs) are prone to destructive electrostatic discharge (ESD) during manufacturing, assembly and testing or in final applications, so that integrated circuits are damaged by static electricity. [0003] ESD is typically produced by the discharge of a high voltage potential (eg, several thousand volts) and results in a short duration (eg, 100 ns) pulse of high current. ESD is usually divided into three categories. The first category is caused by the contact between human and IC. Usually, HBM (human body model) type ESD protection circuit can be made for this type of ESD. The second category is caused by the contact between mechanical equipment and IC. Generally, MM (machine model) type ESD protection circuits can be made for this type of ESD; the third type is caused by the charging of the IC...

AI Technical Summary

Problems solved by technology

figure 1 It is a schematic diagram of an existing CDM ESD protection circuit and a protected functional unit, figure 2 for figure 1 The schematic cross-section of the circuit shown, as figure 1 and figure 2 As shown, the existing CDM ESD protection circuit is implemented by the ESD protection unit 101 (such as a MOS transistor), but with the reduction of the process size, the gate oxide of the MOS transistor of the functional unit is getting thinner and thinner. The functional unit 102 is provided with a discharge channel for the substrate, but because the voltage of the ESD is too high and the time is too short, the gate oxide of the MOS transistor of the functional unit 102 is very easily broken down (for example figure 2 The discharge current shown in I ESD ), so that the functional unit is damaged

[0006] In order to find a better solution, the US Patent No. US6885529B2 discloses a CDM ESD structure that uses a deep well structure to solve the threat of CDM, although this can make the functional units in the isolated N well, thereby greatly reducing the number of functional units The electrostatic charge in the P-well region where it is located, but although the amount of charge is reduced, it can still break down the gate oxide layer of the functional unit MOS transistor and destroy it

Images