Method for manufacturing T-shaped grid structure with U-shaped grid feet

Abstract

The invention discloses a method for manufacturing a T-shaped grid structure with U-shaped grid feet, comprising the following steps: after the source electrode and drain electrode of a device are isolated, preparing a SiNx passivation layer on the surface of the device; utilizing a ZEP520A electron beam photoresist to carry out exposure and development on the device to obtain an etching window; etching the passivation layer to form the structure with the U-shaped grid feet; then etching an AlGaN barrier layer, and obtaining a grid cap by virtue of secondary exposure of double-layer glue; and forming the T-shaped grid structure with the U-shaped grid feet by virtue of evaporation and stripping. In the method, the distribution of an electric field at the near-drain ends of the grid feet of the T-shaped grid can be effectively smoothened, and the intensity of the electric field at the peak is reduced, so that the puncture voltage of the device is improved, and simultaneously a certain inhibiting effect also can be achieved on the short channel effect.

Description

technical field [0001] The invention relates to the field effect transistor (FET) technical field, in particular to a method for manufacturing a U-shaped gate leg and a T-shaped gate structure. Background technique [0002] With the sharp increase in demand for high-frequency applications of field-effect transistors (FETs), it becomes more and more important to increase the cut-off frequency fT of the device. [0003] As an important parameter to characterize the high-speed performance of transistors, the device cut-off frequency f T The approximate formula for is: [0004] f T = v s 2 π L g [0005] where v s is the saturation mobility of carriers, L g is the device gate length. It can be seen that the gate length has a decisive influence on the cut-off frequency of the devi...

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Problems solved by technology

[0009] First, according to the principle of proportional reduction, when the gate length is reduced, the dimensions of the device will be reduced accordingly, and the internal electric field of the device will be larger under the same bias voltage. figure 1 In order to use the 2D device simulation software Atlas to simulate the internal electric field of the device, it can be found that there will be a peak electric field near the drain end of the T-shaped gate, which will cause the device to break down easily, which is not conducive to the application of the device in power

[0010] Second, due to the strong electric field at the gate foot between the gate and the drain, the channel electrons will migrate to the GaN buffer layer, thereby greatly deepening the short channel effect of the device, causing an increase in subthreshold current, threshold voltage drift, and an increase in output conductance. Soft pinch off and other issues

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