Instruction prefetch-based multi-core shared memory control equipment

Abstract

The invention discloses an instruction prefetch-based multi-core shared memory control equipment. The memory control equipment comprises an access instruction buffer module, an instruction resolving and address decoding module, a data read-write control module, a memory control module and a memory interface module. The data read-write control module controls the transmission of data between a memory and an on-chip multi-core processor. The memory control module generates an instruction prefetch marking signal and fetches a next access instruction from the access instruction buffer module in advance, the next access instruction is pre-decoded through the instruction resolving and address decoding module, and the memory control module dynamically selects a page opening or page closing strategy of the memory according to the control information of the prefetch instruction. The memory control equipment can reduce the delay caused by the access of the processor, improve the transmission efficiency of the data and meet the requirement for high-performance storage bus throughput required when the processors work in parallel.

Description

technical field [0001] The invention relates to a data storage control system, in particular to a multi-core shared memory control device based on instruction prefetching. Background technique [0002] Since the 1980s, processor performance has been doubling every 18 months according to Moore's Law, while memory access latency has only increased by 10% every 12 months on average. The performance gap between processor and memory, namely "memory wall", is getting bigger and bigger, and has become the main consideration of parallel real-time multi-core processing system. [0003] At present, dynamic random access memory (DRAM) has been widely used in the field of data storage. Generally, a DRAM control device is used to control reading and writing of the DRAM. The DRAM control device receives the read / write request from the processor, controls the operation of the DRAM through command analysis, writes data into the DRAM or transmits the DRAM data to the processor. figure 1 S...

AI Technical Summary

Problems solved by technology

However, the separation and transmission process of the traditional shared bus is complicated and time-consuming. The slave device needs to re-apply to the bus arbitration for data transmission, and then needs to wait until the master device obtains the right to use the bus, and then completes a data transmission through a new bus transmission cycle.

This will increase the delay of the master processor accessing the slave DRAM memory, reduce the data throughput rate, and limit the performance of parallel p

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