Method for testing trap density of gate dielectric layer of semiconductor device without extending substrate

Abstract

The invention provides a method for testing the trap density of a gate dielectric layer of a semiconductor device without extending a substrate. A test structure for the semiconductor device has a triple-gate structure, gates on both sides are narrow, a gate in the middle is wide, and the three gates control different areas of a channel of the test structure of the semiconductor device to fulfillthe aims of controlling charge trends accurately. By the method for testing traps of the gate dielectric layer of the semiconductor device, the quality of gate dielectrics of the device can be testedsimply, conveniently and conveniently to obtain the distribution condition of the traps under different materials and processes of the gate dielectrics; the test is quick, namely the distribution of the traps of the gate dielectrics of the device can be obtained within short time, so the method is suitable for large-scale automatic tests; and the operation is compatible with that of classical reliability testing (a charge pump), so the method is easy to operate, is suitable for the process monitoring and quality detection of finished products in the process of manufacturing surrounding gate devices of the new generation and is also suitable for other devices without extending substrates.

Description

technical field [0001] The invention relates to a reliability testing method of a semiconductor device, in particular to a method for testing the trap density in a gate dielectric layer of a semiconductor device (such as a surrounding gate device) drawn out without a substrate. Background technique [0002] Semiconductor devices are important components in the manufacture of electronic products. The replacement of semiconductor devices has promoted the development of semiconductor technology and the progress of the semiconductor industry, especially the performance improvement of the central processing unit CPU and memory. Since the end of the last century, the chip manufacturing process has developed very rapidly, from the micron level to today's technology smaller than 32nm. [0003] Under the background of limited improvement of lithography technology and the inability of advanced lithography technology to achieve the purpose of mass production, the continuous reduction ...

AI Technical Summary

Problems solved by technology

The electron and hole traps in the gate dielectric layer of semiconductor devices, that is, some dangling bonds or defects, will cause the threshold voltage of the device to drift, the on-state current will decrease, and serious negative / positive bias temperature instability ( NBTI / PBTI), while increasing the gate leakage current, reducing the reliability and service life of the device, so the research and testing of the traps in the dielectric layer can provide an optimized solution for device manufacturing, and the reliability test of the traps is also a characterization One of the important ways of device working life

[0005] The more accurate trap test method for traditional planar tube devices is mainly the charge pump test. This test requires that the device must have substrate signals; while new devices, such as surrounding gate devices, only have gate, source, and drain. Therefore, the classic charge pump test cannot be applied to the device without the substrate

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