Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof

A technology of chip package and production method, which is applied in the field of multi-circle arrangement carrierless dual-IC chip package, can solve the problems of unsatisfactory ultra-thin packaging products, high density, multi-I/O packaging, etc., and achieve improvement Test yield and reliability, reduce impact, and improve heat dissipation

Active Publication Date: 2011-10-19
TIANSHUI HUATIAN TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The current four-sided flat no-lead package cannot meet the needs of high-density, multi-I/O packaging due to fewer pins, that is, fewer I/Os. At the same time, the bonding wire i

Method used

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  • Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof
  • Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof
  • Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0060] (1), wafer thinning

[0061] Using 8-inch to 12-inch thinning machine, adopts rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 250μm, rough grinding speed: 6μm / s, fine grinding speed: 1.0μm / s; the thickness of the wafer without bumps is 100μm, the rough grinding speed is 2μm / s, the fine grinding speed is 0.8μm / s, and the chip warpage prevention process is adopted.

[0062] (2), scribing

[0063] Wafers ≤8 inches use DISC 3350 double-knife dicing machine, and wafers from 8 inches to 12 inches use A-WD-300TXB dicing machine, and the scribing speed is controlled at ≤10mm / s.

[0064] (3), one-time loading

[0065] IC chips 7 with a carrier frame and no bumps are used for one-time chipping, and conductive adhesive 5 is used for one-time chipping. The equipment and process used for chipping and baking are the same as those of ordinary QFN.

[0066] (4), pressure welding

[0067] Carry out wire bonding for the first ...

Embodiment 2

[0087] (1), wafer thinning

[0088] Using 8-inch to 12-inch thinning machine, using rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 250μm, rough grinding speed: 3μm / s, fine grinding speed: 0.6μm / s; the thickness of the wafer without bumps is 100 μm, the rough grinding speed is 4 μm / s, the fine grinding speed is 0.4 μm / s, and the chip warpage prevention process is adopted.

[0089] (2), scribing

[0090] Wafers ≤8 inches use DISC 3350 double-knife dicing machine, and wafers from 8 inches to 12 inches use A-WD-300TXB dicing machine, and the scribing speed is controlled at ≤10mm / s.

[0091] (3), one-time loading

[0092] Adopt QFN adhesive film (6) and IC chip (7) without concave and convex points, use a core loading machine with adhesive film (6) bonding process, and use a flip chip loading machine for the secondary core of the double chip. The bumps (4) of the IC chip (3) with bumps are dipped with solder (2) and plac...

Embodiment 3

[0114] (1), wafer thinning

[0115] Using 8-inch to 12-inch thinning machine, adopts rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 250μm, rough grinding speed: 3μm / s, fine grinding speed: 0.6μm / s; the thickness of the wafer without bumps is 100 μm, the rough grinding speed is 4 μm / s, the fine grinding speed is 0.4 μm / s, and the chip warpage prevention process is adopted.

[0116] (2), scribing

[0117] Wafers ≤8 inches use DISC 3350 double-knife dicing machine, and wafers from 8 inches to 12 inches use A-WD-300TXB dicing machine, and the scribing speed is controlled at ≤10mm / s.

[0118] (3), one-time loading

[0119] IC chips 7 with a carrier frame and no bumps are used for one-time chipping, and conductive adhesive 5 is used for one-time chipping. The equipment and process used for chipping and baking are the same as those of ordinary QFN.

[0120] (4), pressure welding

[0121] With embodiment 1.

[0122] (5), ...

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PUM

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Abstract

The invention discloses a multi-ring-arranged double-integrated circuit (IC) chip packaging piece and a production method thereof. The multi-ring-arranged double-IC chip packaging piece comprises a multi-ring quad flat no (QFN) lead frame with a carrier, an internal pin, IC chips and a plastic package body. The production method comprises the following steps of: thinning; scribing; adding the chips primarily; performing pressure welding; inversely adding the chips secondarily; filling the bottom and solidifying; performing plastic packaging and post solidifying; printing; separating pins; electroplating; separating products; testing the products; packing; and warehousing. Compared with a single-row lead frame with the same area as the multi-ring QFN lead frame, the multi-ring QFN lead frame increases the pins by over 40 percent, so that the requirements of high density and multiple input/output (I/O) packages are met; the chips are inversely added, so that the packaging piece has a small number of short welding lines, a short heat conduction distance and high radiation capacity; through the inverse addition of the chips, the capacitance and the inductance between protruding points and the pins are far lower than those of the welding lines between a chip welding disc and the pins, so that the influence on high frequency application is reduced; and the thickness of a QFN can be reduced to be below 0.5mm, so that the intersection and the open circuit of the welding lines are avoided and testing qualified rate and testing reliability are improved.

Description

technical field [0001] The invention relates to the technical field of electronic information automation components manufacturing, in particular to four-sided flat leadless IC chip packaging, specifically a multi-circle arrangement carrierless dual IC chip package, and the invention also includes a production method for the package . Background technique [0002] In recent years, with the rapid development of portable electronic components in the field of mobile communications and mobile computers, small packaging and high-density assembly technology has been greatly developed; at the same time, a series of strict requirements have been put forward for small packaging technology, such as requirements The package dimensions should be kept as small as possible, especially if the package height is less than 1 mm. The connection reliability after packaging is improved as much as possible, suitable for lead-free soldering (protecting the environment) and effectively reducing cos...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L21/60
CPCH01L2924/181H01L2924/30107H01L2224/16145H01L2224/32145H01L2224/32245H01L2224/45144H01L2224/45147H01L2224/48247H01L2224/73204H01L2224/73265H01L2224/49433H01L2924/00H01L2924/00014H01L2924/00012H01L2924/00011
Inventor 朱文辉慕蔚李习周郭小伟
Owner TIANSHUI HUATIAN TECH
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