[0048] The invention provides a method for realizing high-resolution analog-to-digital conversion by a low-resolution ADC, and the method comprises the following steps:
[0049] 1) Perform post-processing on the CCD analog signal generated by the FPA (focal plane assembly):
[0050] The purpose of the post-processing of the CCD analog signal generated by the FPA (focal plane assembly) is to make the output signal and the illuminance received by the CCD sensor have the same trend of change, and to suppress the interference introduced in the transmission process and minimize the CCD output signal. Reset noise (kTC noise). usually available figure 2 In order to suppress the interference introduced in the transmission process, the post-processing circuit firstly buffers the received video signal, which is realized by an operational amplifier, and the gain is -1 times. The purpose of the correlated double sampling circuit CDS is to reduce the reset noise (kTC noise) of the CCD output signal as much as possible. It adopts a clamp sampling structure and is realized by an operational amplifier and an analog switch.
[0051] 2) Amplify the processed CCD analog video signal: the specific implementation method is: simultaneously amplifying the processed CCD analog video signal with different magnifications. The purpose of this is to prevent the signal generated by targets of different brightness from being too weak or saturated, and the signal can be amplified by multiple magnifications at the same time. image 3. In the present invention, the analog signal is simultaneously amplified by a gain of 1 and a gain of 2 m Multiplier gain amplification.
[0052] 3) Perform analog-to-digital conversion on the amplified video signal to obtain a low-bit ADC quantization result.
[0053] Perform analog-to-digital conversion on the analog video signal generated in step 2) to obtain a low-bit ADC quantization result. In this patent the 1x gain amplification and 2 m The results of the multiplier gain amplification are simultaneously quantized, and the implementation is as follows image 3 A high-speed dual-channel (n-m)bit ADC is shown for (n-m)bit quantization of the analog video signal.
[0054] In this circuit, the sensitivity of the low-gain ADC is low, that is, the number of electrons corresponding to each ADC quantization unit read out by the camera system is large, which is equivalent to rough quantization of large signals. 2 m The sensitivity of the double-gain ADC is high, that is, the number of electrons corresponding to each ADC quantization unit read out by the camera system is small, which is equivalent to the fine quantization of small signals. Coarse and fine quantization are simultaneously performed on the processed CCD analog video signal, which lays a foundation for the digital comparison in step 4).
[0055] Coarse and fine quantization of the video signal is combined using two different signal processing chains to expand the dynamic range of the CCD camera. The low gain ADC processing chain, after processing by the analog front end, makes the full scale range of the ADC correspond to the full well charge capacity of the CCD (2 n-m gG=S FW ). Due to DR ADC CCD , so the channel gain G>N of the video processing link can be obtained r , that is, the minimum distinguishable signal of the ADC is greater than the readout noise of the CCD. It can be seen from this that the video link has reduced detection sensitivity to small signals, but can coarsely quantify large signals; the high gain ADC processing link, through the analog front end After processing, the channel gain G of the video processing link is less than the read noise (G r ), due to DR ADC CCD , then there must be 2 n gG FW , that is, the full-scale range of the ADC is less than the full-well charge capacity of the CCD. It can be seen that when the video link detects large signals, the ADC is saturated before the CCD is saturated, but it can be refined for small signals;
[0056] 4) Convert the low-level quantization result into a high-level quantization result, and its specific implementation is:
[0057] First, the coarse and fine quantization results generated in step 3) are latched, and 2 m acquisition, respectively calculate the 2 of the coarse quantized value of the pixel m The cumulative sum of the acquisitions is recorded as sum_data 粗量化 and 2 of the quantized value m The cumulative sum of the acquisitions is recorded as sum_data 细量化. Secondly, in the data processing module, the coarse and fine quantization 2 m Accumulation and results of sub-acquisitions are automatically switched. According to the characteristics of the detection target, a threshold is set. First, the pixel is refined to a value of 2 m The cumulative sum result of each acquisition is digitally compared with the threshold value. If the quantized value is 2 m If the cumulative sum result value of the second acquisition is greater than the threshold, take the coarse quantization value of 2 m The cumulative sum result of the acquisitions; if the refinement value is 2 m If the cumulative sum result of the second acquisition is less than the threshold, take the refined value of 2 m Accumulate the sum of the results. Finally, quantize the thickness 2 m The accumulated sum results of the acquisitions are normalized. If the thickness is quantized 2 m Sub-acquisition accumulation and automatic switching of results to select output refinement 2 m The cumulative sum result of the second acquisition, then take the refined value of 2 m The data of high n-m bits of the accumulated sum is collected for the second time, and the low (n-m) bits of the output result are used as the low (n-m) bits of the output result, and the high m bits are filled with zeros. If the thickness is quantized 2 m Select output coarse quantization 2 after acquisition accumulation and automatic switching m Accumulate and accumulate the result for several times, then directly output n-bit coarse quantization 2 m The acquisitions are accumulated. In this way, the coarse and fine quantization results are normalized. The low-resolution ADC realizes high-resolution analog-to-digital conversion through the above-mentioned processing. In the data processing module, several thresholds can be set according to the characteristics of the target detected by the CCD camera. In this patent, a digital circuit is adopted to realize the conversion of the low-bit quantization result into the high-bit quantization result. Latch the coarse and fine quantized values of the low-bit ADC in the FPGA, accumulate and sum, and quantize the coarse and fine 2 m Sub-acquisition accumulation and automatic switching of results and data normalization processing. Its implementation is as Figure 4 shown.
[0058] For ease of explanation, see Figure 5 , collected in each pixel period 2 m point, calculate the 2 of the coarse and fine quantization values of the pixel m Click the cumulative sum. Set a threshold in the FPGA, first compare the accumulated sum of the fine quantized values of the pixel with the threshold, if the accumulated sum of the fine quantized values is greater than the threshold, take the normalized value of the coarse quantized value; If the accumulated sum is less than the threshold, take the normalized value of the refined quantization value. The normalized value of the coarse quantized value is the cumulative sum of the coarse quantized value sum_data 粗量化 The n bits are used as the n bits of the parallel n-bit data; the normalized value of the fine quantized value is the accumulated sum of the fine quantized value sum_data 细量化 The high (n-m) bits are used as the low (n-m) bits of the parallel n-bit data, and the high m bits are filled with zeros.
[0059] 5) Offset correction is performed on the quantization result, and real-time offset correction can be performed on the pixel values collected in step 4). Effectively reduce the bias fluctuation of CCD image data caused by factors such as operating temperature and component aging in the video processing link. When the CCD camera outputs images, the offsets of all pixels have been corrected in real time, which suppresses the floating of offsets. For dual output CCDs, the offsets of the two images are also corrected to the same level. This effectively improves the signal-to-noise ratio and expands the dynamic range of the CCD camera.
[0060] The present invention not only provides a low-resolution ADC to achieve high-resolution analog-to-digital conversion, but also provides a low-resolution ADC to achieve high-resolution analog-to-digital conversion. The system includes a focus plane component FPA The generated CCD analog signal is preprocessed by a preprocessing module, an amplification module is used to amplify the preprocessed CCD analog video signal, the amplified video signal is converted into analog-to-digital, and the low-bit quantization result is converted into a high-bit quantization result. The conversion module; the preprocessing module, the amplification module and the conversion module are electrically connected in sequence. The preprocessing module includes a buffer amplifying unit and a correlated double sampling unit connected with the buffer amplifying unit. The amplification module includes two operational amplifiers with different magnifications. The conversion module includes an analog-to-digital conversion unit, a data processing unit, and an automatic switching unit for coarse and fine quantization results connected with the data processing unit. The data processing unit latches the coarse and fine quantization results at the same time, collects multiple times in each pixel cycle, and calculates the accumulation of the coarse and fine quantization values of the pixel for multiple collections and the coarse and fine quantization results. The automatically switched values perform functions such as data splicing and normalization.
[0061] In order to effectively reduce the offset fluctuation of CCD image data caused by factors such as operating temperature and component aging in the video processing link, the present invention provides a correction for offset correction of high-bit quantization results in addition to the above system. The module, the correction module and the conversion module are connected. The correction module can be any existing commonly used unit or circuit that can perform the function of offset correction.
