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Resistance random access change memory device

A technology of random access memory and variable resistance type, which is applied in the field of variable resistance random access memory devices, and can solve the problems of high integration difficulty, low yield, and low yield, etc.

Inactive Publication Date: 2012-01-25
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0015] However, it is especially necessary to process the bit line to the minimum processing size F. If the power line is similarly processed to the minimum processing size F, the difficulty of integration becomes high and the yield becomes low.
A variable resistance random access memory device capable of preventing yield reduction by using multiple wiring layers and wiring layouts has not yet been proposed

Method used

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  • Resistance random access change memory device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0068] memory cell structure

[0069] Figure 1A and Figure 1B is an equivalent circuit diagram of a memory cell of an embodiment of the present invention. Notice, Figure 1A Indicates the direction of the write current Iw, Figure 1B Indicates the direction of the erase current Ie, Figure 1A and Figure 1B The memory cell structure is the same.

[0070] Figure 1A and Figure 1B The shown memory cell MC has a variable resistance element Rcell and an access transistor AT.

[0071] One end of the variable resistance element Rcell is connected to the power supply line SL, and the other end is connected to the source of the access transistor AT. The drain of access transistor AT is connected to bit line BL, and the gate is connected to word line WL.

[0072] figure 2 The device structure of the corresponding parts of two adjacent memory cell parts is shown. figure 2 It is a schematic cross-sectional view without occlusion. in addition, figure 2 Vacant portions not ...

example 1

[0164] Figure 14 A modified example of the processed shape of the power supply line SL is shown.

[0165] Such as Figure 14 As shown, the processed shape of the power supply line SL may be formed to be wider in a portion of the power supply line contact portion SLC and narrower in other portions. In this processed shape, there is an advantage that the average width of the space is widened, the removability of the wiring material (removability of the etched portion) is improved, whereby the yield is made higher.

[0166] Thus, the line width of the power supply lines in the row direction can be made smaller than twice the pitch of the power supply lines in the row direction.

example 2

[0168] Figure 15 A modified example of the overlapping width of the power line contact portion SLC and the power line SL is shown.

[0169] Such as Figure 15 As shown, if the upper surface of the power supply line contact portion SLC is not completely covered by the power supply line SL, the characteristics of the memory will not be damaged. According to the structure of the variable resistance element Rcell, the variable resistance element Rcell ( Figure 15 not shown) is smaller than the size of the power line contact portion SLC.

[0170] Thus, the line width of the power supply lines in the row direction can be made smaller than twice the pitch of the power supply lines in the row direction.

[0171] Driving Circuit and Operation Example

[0172] Figure 16 Circuits showing main parts of the BL driver 10 and the SL driver 12 connected to the memory cell array 1 .

[0173] Figure 16 The shown driving circuit (10, 12) includes five NAND circuits NA...

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PUM

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Abstract

A resistance random access change memory device includes: a memory cell array in which plural memory cells having current paths with series-connected access transistors and variable resistive elements are two-dimensionally arranged; plural bit lines that connect one ends of the current paths; plural source lines that connect the other ends of the current paths; and plural word lines that control conduction and non-conduction of the access transistors, wherein bit line contacts are shared between two memory cells to which the word lines are adjacently provided, and pairs of memory cells are formed, all of the pairs of memory cells connected to the adjacent two bit lines are connected to the corresponding source lines via individual source line contacts, and the source lines are formed by a wiring layer upper than that of the bit lines with a larger pitch than that of the bit lines.

Description

[0001] Cross References to Related Applications [0002] The present application contains subject matter related to the disclosure of Japanese Priority Patent Application JP 2010-133295 filed in the Japan Patent Office on Jun. 10, 2010, the entire content of which is hereby incorporated by reference. technical field [0003] The present invention relates to a resistance variable random access memory device having a memory cell having an access transistor and a variable resistance element connected in series. Background technique [0004] Nonvolatile memory devices that are used by applying a pre-charge voltage to a bit line and reading the difference between the discharge rates are well known. [0005] The (flash) EEPPRPM is one of the nonvolatile semiconductor memory devices to which this reading method is applicable. [0006] On the other hand, in order to replace the FG type (flash) EEPROM, a resistance variable random access memory device is being emphasized as a nonvol...

Claims

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Application Information

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IPC IPC(8): G11C7/18H01L27/24
CPCG11C13/00H01L45/085G11C2013/0069G11C2213/82H01L27/2436G11C13/0026H01L45/1266G11C2213/79H01L45/1233G11C13/0069H10B63/30H10B63/82H10N70/245H10N70/826H10N70/8416H10N70/883
Inventor 北川真椎本恒则吉原宏
Owner SONY CORP
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