Static random access memory (SRAM) circuit device employing hierarchical bit lines and two-stage sensitive amplifier

Abstract

The invention relates to a static random access memory (SRAM) circuit device employing hierarchical bit lines and a two-stage sensitive amplifier. The circuit device is divided into subarrays; in each subarray, each local bit line is hung with a SRAM unit correspondingly by using divided bit line number; a first stage sensitive amplifier has a latch type structure; two input nodes and output nodes of inverters which are crossed and coupled are respectively driven for a global bit line through a P-channel metal oxide semiconductor (PMOS) transistor, so a signal after amplification of local bitlines is not required to be buffered and used for directly driving the global bit line. Compared with the conventional scheme, the speed can be increased. A second stage sensitive amplifier adopts a pair of complementary differential amplifiers, starts working before the first stage sensitive amplifier is opened, responses to changes of the global bit line, and amplifies differential data on the global bit line to full amplitude for output. A complementary structure is adopted in the invention and favorable for latching of the data and final driving output; compared with the traditional structure, the circuit employing the hierarchical bit lines and a two-stage amplification mechanism has the advantages that: the access delay is reduced by 15 percent, and the speed of a SRAM is effectively increased.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit devices, in particular to an SRAM circuit device using hierarchical bit lines and two-stage sensitive amplifiers. Background technique [0002] Static random access memory (SRAM) has high speed and low power consumption in semiconductor memory, and is widely used in SoC systems. Due to its fast access speed, SRAM is often used in high-speed Cache that communicates directly with the CPU. [0003] At present, for large-capacity SRAMs, the designer's design solution to increase the access speed is mainly to reduce the discharge time of the bit line in the critical path. The bit line discharge time is closely related to the capacitance of a single bit line, and the bit line capacitance is proportional to the number of mounted six-transistor units. [0004] Currently, techniques of dividing smaller sub-arrays and dividing bit lines are commonly used to reduce the load capacit...

AI Technical Summary

Problems solved by technology

For larger-capacity SRAM chips, this shortcoming becomes more prominent. The simulation results show that the global interconnection delay of large-capacity SRAM chips accounts for more than 20% of the overall access time.

Moreover, the first-stage sense amplifier needs to drive such a long global data line, and buffer stages and larger drivers must be added, which will further increase the read delay.

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