Method and system for extracting parasitic parameter

Abstract

The invention discloses a method for extracting a parasitic parameter, which comprises the following steps of: dividing a layout of integrated circuit design into a plurality of subareas; arranging the geometry isomorphism subarea into the same isomorphism list; carrying out the extraction of the parasitic parameter on at least one subarea in each isomorphism list; calculating according to the geometrical relationship among the subareas in the isomorphism list and the parasitic parameter of the extracted subarea to obtain the parasitic parameters of other subareas in the isomorphism list; andcombining the parasitic parameters of all the subareas to obtain the parasitic parameter of the whole integrated circuit design. By combining the parasitic parameter extracting task, the method has the advantages of not carrying out parasitic parameter extraction on the whole layout area, reducing the extracting quantity of the parasitic parameters in the integrated circuit layout so as to improve the extracting speed of the parasitic parameters and shortening the cycle of the integrated circuit design.

Description

technical field [0001] The invention relates to the field of integrated circuit design automation, and more specifically, to a method and system for extracting parasitic parameters. Background technique [0002] The design of interconnection lines is an important link in integrated circuit design. As the integrated circuit manufacturing process enters the 65-45nm process node, the wavelength of light used for exposure is much larger than the size of the ideal graphics in physical layout design and the distance between graphics. The spacing, interference and diffraction effects of light waves make there is a big difference between the ideal graphics designed for physical graphics and physical layouts produced by actual lithography, and the shape and spacing of actual graphics change greatly, even affecting the performance of the circuit. Therefore, while the interconnection wires (metal layers) realize the electrical connection function, it is necessary to consider the electr...

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Problems solved by technology

[0005] However, the current integrated circuit design shows the trend of system-on-chip (SOC) and network-on-chip (NOC) in scale. When the number of devices is more than several times, the corresponding physical layout data reaches dozens of Gb (10 9 Bits), or even hundreds of Gb, using the existing technology to perform full-chip 3D lithography simulation and 3D parasitic parameter extraction is extremely slow, which is not feasible in practical applications, and the speed of parasitic parameter extraction affects the design cycle of integrated circuits. One of the important factors is that the traditional serial and parallel parasitic parameter extraction requires detailed and complicated simulation calculations for each tiny area of ​​the integrated circuit layout, so the speed is relatively slow, which restricts the improvement of design efficiency

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