LDMOS ESD(Laterally Diffused Metal Oxide Semiconductor Electro-Static Discharge) structure

Abstract

The invention discloses an LDMOS ESD(Laterally Diffused Metal Oxide Semiconductor Electro-Static Discharge) structure comprising a gate region, a drain region and a source region, wherein an interdigitated STI(Shallow-Trench Isolation) structure is arranged in the source region, so that the flow direction of the electrostatic leakage current of the LDMOS ESD is of a square-wave form. Therefore, the effective channel length is increased while the actual channel length is not increased, and the effective channel resistance is increased, thereby further increasing the sustaining voltage and enhancing the antistatic effect of the LDMOS ESD.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an LDMOS ESD structure which can effectively reduce device size. Background technique [0002] As the level of integrated circuit manufacturing technology enters the deep submicron era of integrated circuit line width, the feature size of CMOS technology continues to shrink, and the ability of transistors to withstand high voltage and high current continues to decrease. Deep submicron CMOS integrated circuits are more susceptible to electrostatic shock failure, resulting in a decrease in product reliability. [0003] Static electricity is ubiquitous in the process of chip manufacturing, packaging, testing and use. The accumulated static charge is released in nanoseconds to microseconds with a current of several amperes or tens of amperes. The instantaneous power is as high as hundreds of kilowatts, and the discharge energy It can reach millijoules, and the destructio...

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Problems solved by technology

[0017] The purpose of the present invention is to provide an LDMOS ESD structure to solve the problem that the existing LDMOS ESD increases the antistatic ability by increasing the channel length L, which causes the device size of the LDMOS ESD to increase, thereby increasing the IC design cost.

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