Manufacturing method of twin-transistor and zero-capacitance dynamic RAM (Random Access Memory)

A dual-transistor and MOS transistor technology, applied in the field of preparation of dual-transistor zero-capacitance dynamic RAM, can solve problems such as unresolved manufacturability

Active Publication Date: 2012-04-18
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to enable the floating body charge of T1 to quickly drive T2, it is required to reduce the parasitic capacitance of T2 as much as possible. Therefore, it is required that the source drain of T2 and the gate have a larger distance (Underlap) to reduce the parasitic capacitance between the gate and source drain of T2. This FBGC 2T DRAM structure has certain uniqueness, but it does not solve the manufacturability (DFM, Design for Manufacturability) problem, that is, how to effectively realize the T1 source, drain and gate different from the conventional CMOS process through self-alignment in the process There is a large overlap and a large distance between the source and drain of T2 and the gate

Method used

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  • Manufacturing method of twin-transistor and zero-capacitance dynamic RAM (Random Access Memory)
  • Manufacturing method of twin-transistor and zero-capacitance dynamic RAM (Random Access Memory)
  • Manufacturing method of twin-transistor and zero-capacitance dynamic RAM (Random Access Memory)

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preparation example Construction

[0051] The present invention is a method for preparing silicon-on-insulator gate-back dual-transistor zero-capacitance dynamic RAM with manufacturability design, wherein the dual transistors are two cascaded MOS transistors T1 and T2 formed on a common substrate, specifically Including preparatory procedures and subsequent procedures, wherein the preparatory procedures include:

[0052] Thin oxide layers are respectively formed on the channel surfaces between the respective source and drain electrodes of T1 and T2;

[0053] The respective gate trenches of T1 and T2 are respectively formed by additional sample gate wet etch-back on the thin oxide layer, and the high dielectric layer and the metal oxide above it are respectively formed in the respective gate trenches of T1 and T2 layer of dielectric material. Optionally, the high dielectric layer and the metal oxide dielectric material layer can also be formed first when the sample gate is prepared, and not removed when the add...

Embodiment 1

[0059] Embodiment one , when the two cascaded MOS transistors T1 and T2 are all NMOS structures, specifically include the following steps:

[0060] Such as Figure 3A As shown, the gate trenches of T1 and T2 are respectively formed by additional sample gate wet etch back, and the gate dielectric layers of T1 and T2 include high dielectric layer 2 (HK layer) and metal oxide dielectric material above it Layer 3 (Cap layer), a thin oxide layer 1 can optionally be grown under the high dielectric layer 2, and the gate dielectric layer of T1 and T2 can be formed after the sample gate is wet-etched back, or it can be formed during the preparation of the sample gate Formed and not removed during sample gate wet etch back;

[0061] Such as Figure 3B As shown, perform photolithography, open the window in the T1 region, close the window in the T2 region, perform an angle tilt, rotate 180 degrees, and then perform bidirectional ion implantation so that the gate is close to the source...

Embodiment 2

[0066] Embodiment two, When the two cascaded MOS transistors T1 and T2 are all PMOS structures, the following steps are specifically included:

[0067] Such as Figure 5A As shown, the gate trenches of T1 and T2 are respectively formed by additional sample gate wet etch back, and the gate dielectric layers of T1 and T2 include high dielectric layer 2 (HK layer) and metal oxide dielectric material above it Layer 3 (Cap layer), a thin oxide layer 1 can optionally be grown under the high dielectric layer 2, and the gate dielectric layer of T1 and T2 can be formed after the sample gate is wet-etched back, or it can be formed during the preparation of the sample gate Formed and not removed during sample gate wet etch back;

[0068] Such as Figure 5B As shown, perform photolithography, open the window in the T1 area, close the window in the T2 area, perform an angle tilt, rotate 180 degrees, and then perform bidirectional ion implantation to make the gate close to the source an...

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Abstract

The invention discloses a manufacturing method of a twin-transistor and zero-capacitance dynamic RAM (Random Access Memory), aiming at providing the manufacturing method of the twin-transistor and zero-capacitance dynamic RAM which is manufactured by adopting a silicon of insulator-based gate-last process and has a design for manufacturability. In the process, the characteristics different from the characteristics of greater Overlap between a T1 source/drain electrode and a gate and greater distance Underlap between a T2 source/drain electrode and the gate in a conventional CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process are effectively achieved by self aligning; the manufacturing method is suitable for manufacturing of an integrated circuit in the gate-last process of a high-dielectric-constant oxidation layer metal gate of below 45nm; and by adjusting work functions of the gates of the T1 and the T2, which are close to the source electrode and the drain electrode, or doping types of channel regions at the lower parts of the gates, which are close to the source electrode and the drain electrode through ion implantation, the channel regions in the channel regions of the T1, which are close to the source electrode and the drain electrode, are inverted to be the same types with the source region and the drain region under the condition of no increase of the pressure of the gates and diffusion regions below the gates of the source electrode and the drain electrode of the T2 are inverted into the opposite types of the source region and the drain region under the condition of no increase of the pressure of the gates.

Description

technical field [0001] The present invention generally relates to the technical field of semiconductor manufacturing, and more specifically, the present invention relates to a method for preparing a dual-transistor zero-capacitance dynamic RAM based on a silicon-on-insulator gate-last process with manufacturability design. Background technique [0002] As semiconductor integrated circuits enter the era of higher-level technology, the traditional One Transistor One Capacitor (1T1C) structure DRAM is made of capacitors and transistors. Capacitors are used to store data and transistors are used as data channels. The switching components of the system undoubtedly aggravate the complexity of the manufacturing process, especially the difficulty of preparing capacitors with high integration density and low leakage current is becoming more and more difficult. Therefore, the current research on zero-capacitance dynamic RAM or capacitive dynamic RAM (Zero-Capacitor RAM or Capacitorles...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8242H01L21/84H01L21/266
Inventor 黄晓橹颜丙勇陈玉文邱慈云
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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