Manufacturing method of twin-transistor and zero-capacitance dynamic RAM (Random Access Memory)

Abstract

The invention discloses a manufacturing method of a twin-transistor and zero-capacitance dynamic RAM (Random Access Memory), aiming at providing the manufacturing method of the twin-transistor and zero-capacitance dynamic RAM which is manufactured by adopting a silicon of insulator-based gate-last process and has a design for manufacturability. In the process, the characteristics different from the characteristics of greater Overlap between a T1 source / drain electrode and a gate and greater distance Underlap between a T2 source / drain electrode and the gate in a conventional CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process are effectively achieved by self aligning; the manufacturing method is suitable for manufacturing of an integrated circuit in the gate-last process of a high-dielectric-constant oxidation layer metal gate of below 45nm; and by adjusting work functions of the gates of the T1 and the T2, which are close to the source electrode and the drain electrode, or doping types of channel regions at the lower parts of the gates, which are close to the source electrode and the drain electrode through ion implantation, the channel regions in the channel regions of the T1, which are close to the source electrode and the drain electrode, are inverted to be the same types with the source region and the drain region under the condition of no increase of the pressure of the gates and diffusion regions below the gates of the source electrode and the drain electrode of the T2 are inverted into the opposite types of the source region and the drain region under the condition of no increase of the pressure of the gates.

Description

technical field [0001] The present invention generally relates to the technical field of semiconductor manufacturing, and more specifically, the present invention relates to a method for preparing a dual-transistor zero-capacitance dynamic RAM based on a silicon-on-insulator gate-last process with manufacturability design. Background technique [0002] As semiconductor integrated circuits enter the era of higher-level technology, the traditional One Transistor One Capacitor (1T1C) structure DRAM is made of capacitors and transistors. Capacitors are used to store data and transistors are used as data channels. The switching components of the system undoubtedly aggravate the complexity of the manufacturing process, especially the difficulty of preparing capacitors with high integration density and low leakage current is becoming more and more difficult. Therefore, the current research on zero-capacitance dynamic RAM or capacitive dynamic RAM (Zero-Capacitor RAM or Capacitorles...

AI Technical Summary

Problems solved by technology

In order to enable the floating body charge of T1 to quickly drive T2, it is required to reduce the parasitic capacitance of T2 as much as possible. Therefore, it is required that the source drain of T2 and the gate have a larger distance (Underlap) to reduce the parasitic capacitance between the gate and source drain of T2. This FBGC 2T DRAM structure has certain uniqueness, but it does not solve the manufacturability (DFM, Design for Manufacturability) problem, that is, how to effectively realize the T1 source, drain and gate different from the conventional CMOS process through self-alignment in the process There is a large overlap and a large distance between the source and drain of T2 and the gate

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