One-transistor dynamic random access memory (DRAM) unit based on silicon-germanium silicon heterojunction, and method for preparing one-transistor DRAM unit

Abstract

The invention discloses a one-transistor dynamic random access memory (DRAM) unit based on a silicon-germanium silicon heterojunction and a method for preparing the one-transistor DRAM unit. The method for preparing the single-transistor DRAM unit comprises the following steps of: forming a SiGe epitaxial layer in the top layer of a silicon wafer on an insulator; performing a surface dry oxidization process on the SiGe epitaxial layer so as to form a first conductive type SiGe body region, wherein the dry oxidization process is not stopped until a valence band position of the first conductive type SiGe body region is higher than that of the material of the top layer of the silicon wafer on the insulator according to a mole ratio of the germanium content in the first conductive type SiGe body region; and forming an N-channel metal oxide semiconductor (NMOS) transistor comprising the heterojunction based on silicon-germanium silicon in the silicon wafer on the insulator, wherein the NMOS transistor is a single transistor. The 1T-DRAM unit can effectively reduce the working voltage and increase the balance of output current between readings '0' and '1', namely the signal margin is increased.

Description

technical field [0001] The present invention generally relates to a method for preparing a capacitive (Capacitorless) dynamic random access memory (DRAM), in particular to a single-transistor dynamic random access memory (1T-DRAM) cell structure based on a silicon-germanium-silicon heterojunction and its preparation method. Background technique [0002] As the feature size of semiconductor integrated circuit devices continues to shrink, for traditional single transistor / single capacitor (1T / 1C) embedded (embedded) DRAM cells, the capacitance generally includes stack capacitors or deep trenches. deep-trench capacitor, etc., in order to obtain sufficient storage capacity (generally requires 30fF / unit), the capacitance manufacturing process of the DRAM unit will become more and more complicated, and the compatibility with the logic device process will become more and more Difference. Therefore, a capless DRAM with good compatibility with logic devices will have a good develop...

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Problems solved by technology

[0006] Therefore, the existing 1T-DRAM still has the following defects: for example, the operating voltage of the transistor is too high, and the difference between the source and drain currents between the read "0" and read "1" states is small, resulting in signal margins The degree is small, which is not conducive to the working stability of DRAM, etc.

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