Single-transistor DRAM (dynamic random access memory) unit based on source heterojunction and preparation method thereof

Abstract

The invention relates to a single-transistor DRAM (dynamic random access memory) unit based on source heterojunction and a preparation method thereof. The method comprises the following steps: forming an SiGe epitaxial layer in the top layer of an SOI (silicon-on-insulator) wafer; carrying out surface dry-oxygen oxidation technique on the SiGe epitaxial layer to form a first conducting SiGe region, wherein the surface dry-oxygen oxidation technique is not stopped until the mol ratio of the germanium content in the first conducting SiGe region enables the valence band position of the first conducting SiGe region to be higher than the valence band position of the top layer material of the SOI wafer; and forming an NMOS (n-channel metal-oxide-semiconductor field-effect transistor), including source heterojunction, in the SOI wafer, wherein the NMOS is the single-transistor, the first conducting SiGe region comprises a source region and a drain region, the source region is positioned below the gate of the NMOS to be formed, and the drain region is positioned on one side of the source region and is corresponding to the drain region of the NMOS. The invention can effectively lower the working voltage, and increase the signal margin.

Description

technical field [0001] The present invention generally relates to a preparation method of a capacitorless dynamic random access memory (DRAM), and in particular to a single transistor dynamic random access memory (1T-DRAM) cell structure based on a source body heterojunction and the same Preparation. Background technique [0002] As the feature size of semiconductor integrated circuit devices continues to shrink, for traditional single-transistor / single-capacitor (1T / 1C) embedded DRAM cells, the capacitors generally include stack capacitors or deep trenches. In order to obtain sufficient storage capacitance (generally 30fF / cell), the capacitor preparation process of the DRAM cell will become more and more complicated, and the compatibility with the logic device process will also become more and more Difference. Therefore, a capacitorless DRAM with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM in v...

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Problems solved by technology

[0006] Therefore, the existing 1T-DRAM still has the following defects: for example, the operating voltage of the transistor is too high, and the difference between the source and drain currents in the state of reading "0" and reading "1" is small, resulting in signal margin Small, not conducive to the working stability of DRAM and other issues

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