Formation method of salicide

Abstract

The invention discloses a formation method of salicide. The method comprises the following steps: depositing a salicide block oxide and then carrying out heat baking; etching the salicide block oxide; after a semiconductor substrate surface or a grid structure corresponding to a contact hole formation area, depositing a metal; finally, carrying out rapid annealing processing and forming the salicide on the exposed semiconductor substrate surface or the grid structure surface. By using the method disclosed in the invention, differences of resistance values in unit areas of the salicide block oxide in a same batch of products can be reduced.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a method for forming a metal silicide. Background technique [0002] With the development of semiconductor manufacturing technology, the reduction of the size of semiconductor devices has brought about the improvement of relative contact resistance. In order to reduce the relative contact resistance, the formation process of metal silicide (salicide) has been widely used. Figure 1a ~ Figure 6a It is a process sectional schematic diagram of a method for forming a metal silicide in the prior art, and the method mainly includes: [0003] Step 101, see Figure 1a A semiconductor substrate 1001 is provided, a gate oxide layer 1002 is grown on the surface of the semiconductor substrate 1001, polysilicon 1003 is deposited, and a gate structure is formed by photolithography, etching, ion implantation and other processes. [0004] In this step, the gate oxide layer 1002 is first grown; then, ...

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Problems solved by technology

[0019] However, in practical applications, when depositing the metal silicide barrier layer in step 105, due to the performance difference of different machines, when the step of depositing the metal silicide barrier layer is performed on wafers located on different machines, the deposition rate is not stable. are exactly the same, which may make the density of the metal silicide barrier layer significantly different between different wafers in a batch of products, and when the subsequent step 106 is performed for rapid annealing, the gate, lightly doped drain, lightly doped Ions implanted in the doped source, drain, and source will diffuse out to some extent through the barrier metal silicide layer into the barrier metal silicide layer due to the induction of the barrier metal silicide layer between different wafers. If the density is significantly different, the number of ions diffused to the metal silicide barrier layer is also quite different, which makes the performance of the same batch of products vary greatly. It can be found through measurement that this performance difference is mainly reflected in the metal silicide of the same batch of products. The resistance value per unit area of ​​the barrier layer varies greatly. In principle, the more ions diffused into the metal silicide barrier layer, the greater the resistance value per unit area of ​​the metal silicide barrier layer.

However, in practical applications, we expect the resistance value per unit area of ​​the metal silicide barrier layer of the same batch of products to be consistent. It can be seen that the methods of the prior art are difficult to achieve the above purpose

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