Method for generating photodetector isolation in image sensors

Abstract

The invention relates to a method for generating photodetector isolation in image sensors. Shallow trench isolation regions are disposed in an n-type silicon semiconductor layer laterally adjacent to a collection region of a photodetector and laterally adjacent to a charge-to-voltage conversion region. The shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer and a first dielectric structure disposed along an interior bottom and sidewalls of each trench. A second dielectric structure is disposed over the pinning layer. The dielectric structures include a silicon nitride layer disposed over an oxide layer. An n-type isolation layer is disposed along only a portion of the exterior bottom of the trench and the exterior sidewall of the trench immediately adjacent to the photodetector. The n-type isolation layer is not disposed along the remaining portion of the bottom or the opposing exterior sidewall of the trench.

Description

technical field [0001] This disclosure relates to image sensors for use in digital cameras and other types of image capture devices, and more particularly, to complementary metal-oxide-semiconductor (CMOS) image sensors. Still more particularly, the present invention relates to photodiode isolation in CMOS image sensors and a method for producing such isolation. Background technique [0002] Image sensors capture images using thousands to millions of pixels, usually arranged in an array. FIG. 1 depicts a top view of a pixel commonly used in a CMOS image sensor according to the prior art. Pixel 100 includes a photodetector (PD) 102 that collects charge in response to incident light. Before the charge is read out from the photodetector 102, an appropriate signal is applied to the gate (RG) of the reset transistor via contact 104 to reset the charge-to-voltage conversion region (FD) 106 to a known potential VDD. Charge is then transferred from the photodetector 102 to the ch...

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Problems solved by technology

[0007] The shallow n+ implantation of the isolation layer 114 can lead to an increase in the peripheral capacitance of the charge-to-voltage conversion region 106 and can result in a higher dark due to the p+ / n+ diode junction formed by the n-type isolation layer and the p-type charge-to-voltage conversion region 106. current or point defect

In addition, n-type isolation layer 114 laterally adjacent to one or more transistors (eg, amplifier transistors (SF)) in pixel 100 can reduce the effective width of the transistors

This can result in a narrow channel effect and requires a wider transistor design which in turn reduces the fill factor of the pixel

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