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2-bit multiplier with set/mos hybrid structure based on threshold logic

A technology of threshold logic and hybrid structure, applied in logic circuits, instruments, electrical digital data processing, etc., can solve the problems of not being able to meet the performance requirements of integrated circuits, consume more CMOS transistors, and complex circuit structures, etc., to reduce the number of tubes, Effects of reduced power consumption and simplified circuit structure

Active Publication Date: 2014-10-01
FUZHOU UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Traditional multipliers based on CMOS technology are composed of multi-stage full adders and AND gates, which consume more CMOS transistors, and the circuit structure is complex and the integration level is not high.
These characteristics make the traditional multiplier design method unable to meet the increasing performance requirements of integrated circuits

Method used

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  • 2-bit multiplier with set/mos hybrid structure based on threshold logic
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  • 2-bit multiplier with set/mos hybrid structure based on threshold logic

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Embodiment Construction

[0015] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0016] Such as image 3 As shown, the present embodiment provides a SET / MOS hybrid structure 2-bit multiplier based on threshold logic, which is characterized in that it includes an exclusive OR gate, four signal sources, three two-input threshold logic gates, a three-input threshold logic gate and a four-input threshold logic gate; the first signal source A of the four signal sources 0 Connected with the first end of the first two-input threshold logic gate, the first end of the third two-input threshold logic gate, and the first end of the four-input threshold logic gate; the second signal source B 0 Connected with the second end of the first two-input threshold logic gate, the second end of the second two-input threshold logic gate, and the second end of the four-input threshold logic gate; the third signal source A 1 Connected with the first end o...

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Abstract

The invention relates to the technical field of integrated circuits, in particular to a semiconductor field-effect transistor / metal-oxide-semiconductor (SET / MOS) mixed structure 2-bit multiplier which only comprises five threshold logic gates, one phase inverter and one exclusive-OR gate, and consumes a total of seven P-channel metal oxide semiconductor (PMOS) tubes, seven N-channel metal oxide semiconductor (NMOS) tubes and six semiconductor field-effect transistors (SETs). The average power consumption of a whole circuit is only 46nW. Compared with a complementary metal-oxide-semiconductor (CMOS) multiplier based on Boolean logic, the number of tubes is greatly reduced, the power consumption is significantly reduced, the structure of the circuit is further simplified, the area of a chip is favorably saved, the integration of the circuit is improved, and the SET / MOS mixed structure 2-bit multiplier based on threshold logic is expected to be widely applied to microprocessors, digital signal processors and image engines.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a threshold logic-based SETMOS hybrid structure 2-bit multiplier composed of nanometer devices. Background technique [0002] As the feature size of integrated circuits enters deep sub-micron, the resistance to further development comes not only from the manufacturing process, but also from the physical limitations brought about by small-scale and high-density integration, such as short channel effects, strong field effects, leakage Pole leads to the barrier lowering effect and so on. As an important combinational logic circuit, the multiplier is widely used in microprocessors, digital signal processors and image engines. Traditional multipliers based on CMOS technology are composed of multi-stage full adders and AND gates, which consume more CMOS transistors, and the circuit structure is complex and the integration level is not high. These characteristics make the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/523H03K19/094
Inventor 魏榕山陈锦锋陈寿昌何明华
Owner FUZHOU UNIV