Two-stage FPGA (field programmable gate array) pipeline configuration circuit

Abstract

The invention belongs to the technical field of FPGA devices, and particularly relates to a two-stage FPGA pipeline configuration circuit. The circuit utilizes two FIFO (first input first output) modules as buffers between a configuration interface and configuration control logic, and the configuration control logic comprises a configuration register set, a global configuration control state machine, a bit stream analysis module, a configuration address generation module, a frame ECC (error correction code) circuit, a CRC (cyclic redundancy check) 32 circuit and the like. A download data path is transmitted to an FPGA by the download FIFO module via a download data register, and a readback data path is transmitted to a readback FIFO module by the FPGA via a readback data register. The circuit with the structure utilizes two-stage pipelines to control download and readback of data, feedback handshaking signals with the flow direction opposite to the flow direction of the data are absent in the data paths, the data are read by the first stage of each pipeline at a highest speed rate, and speed and throughput rate of download and readback of the data can be greatly increased by the aid of the circuit with the structure.

Description

technical field [0001] The invention belongs to the technical field of FPGA devices, in particular to a high-speed and high-throughput FPGA pipeline configuration circuit. technical background [0002] The function of the FPGA (Programmable Logic Gate Array) configuration circuit or programming download circuit is to download the configuration bit stream to the FPGA internal programming point. The user transmits the configuration bit stream to the configuration circuit according to a certain interface timing through the configuration interface, and the configuration circuit writes these data into the internal programming point according to a certain method. Therefore, the configuration of the configuration circuit largely determines the rate at which the bitstream is downloaded. The pipelined configuration structure designs the data download path and the data readback path into a pipeline form. Data is transmitted in a single direction, and the corresponding control signals...

AI Technical Summary

Problems solved by technology

[0005] The current existing structure does not make strict requirements on the configuration data path, nor does it specify the corresponding ...

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