Heterogeneous design method for optimizing embedded STT- RAM (Spin-Torque Transfer Random Access Memory) performances and hardware consumption

Abstract

The invention discloses a heterogeneous design method for optimizing embedded STT-RAM (Spin-Torque Transfer Random Access Memory) performances and hardware consumption. Storage characteristics of the STT-RAM are changed by changing the area of a free layer, the size of an nMOS transistor and the size of a memory array of a magnetic tunneling junction (MTJ) on a memory unit of the STT- RAM, and memory modules with different storage characteristics can be integrated in a same chip. Under the condition that the STT-RAM technological process is not changed, the method adopts different structures and circuits to design the STT- RAM modules with completely different storage characteristics, so as to respectively meet various storage requirements of an operation processing unit. Therefore, requirements of a system on chip can be met only by adopting the STT- RAM technology, the storage chip usage is reduced, the capacity of the memory integrated on the system on chip is increased, and furthermore, the STT- RAM performances and the hardware consumption are optimized.

Description

technical field [0001] The present invention relates to a novel memory technology and a computer storage architecture design method, in particular to a heterogeneous design strategy and method for optimizing the overall performance and performance of embedded spin-torque transfer random access memories in high-performance processors and mobile terminal SoC chips Hardware cost. Background technique [0002] Spin-Torque Transfer Random Access Memory (STT-RAM for short), as a new generation of magnetoresistive random access memory (Magnetic RAM) technology, is one of the most concerned new storage technologies in the industry. Compared with traditional memory technology, STT-RAM has many advantages such as non-volatility, high storage density, strong scalability, fast read and write speed, and low static power consumption. and the potential of Universal Memory in high-performance processors. [0003] Adopting STT-RAM as the embedded memory of system-on-chip and processor has ...

AI Technical Summary

Problems solved by technology

However, the programming control of flash memory is complicated, and the access speed is slow, which brings a certain complexity to the design of the system chip

[0009] A variety of memory chips with completely different processing technologies bring additional packaging and system integration costs to the electronic system, and at the same time become the main technical constraint for system performance improvement

Although STT-RAM, as a memory technology with general characteristics, is expected to provide a complete storage solution for SoCs, it is difficult for STT-RAM using traditional isomorphic design strategies to meet the diverse storage requirements of SoCs.

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