Transistor and making method thereof

A fabrication method and transistor technology, which are applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, electrical components, etc., can solve the problems of high junction capacitance and junction current, and unsatisfactory transistor performance, so as to reduce junction leakage current and reduce Junction capacitance, the effect of improving performance

Active Publication Date: 2012-08-01
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In practice, it is found that the short channel effect of the transistor produced by the existing method is obvious, the junction capacitance and junction current between the source / drain region and the semiconductor substrate are relatively high, and the performance of the transistor is not ideal

Method used

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  • Transistor and making method thereof
  • Transistor and making method thereof
  • Transistor and making method thereof

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Embodiment Construction

[0048] The short channel effect of the transistor manufactured by the existing method is obvious, and the performance of the device is not ideal. With the development of semiconductor technology, ultra-shallow junction technology is applied to make the source region and the drain region, and the ion lateral diffusion between the source region and the drain region is more serious, which makes the short channel effect more obvious, and the source region and the drain region There is a large junction capacitance and junction leakage current between the drain region and the semiconductor substrate, which reduces the response speed of the device and affects the performance of the device.

[0049] In order to solve the above problems, the inventor proposes a method for manufacturing a transistor, including: providing a semiconductor substrate, a spacer layer is formed on the surface of the semiconductor substrate, and the material of the spacer layer is the same as that of the semico...

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Abstract

The invention provides a transistor and a making method thereof. The making method comprises providing a semiconductor substrate, wherein a surface of the semiconductor substrate is provided with a spacing layer; forming a blocking side wall at a side of the spacing layer; forming an epitaxial layer on the surface of the semiconductor substrate of both sides of the spacing layer formed on the blocking side wall, and the surface of the epitaxial layer is higher than the top of the blocking side wall; carrying out a first ion implantation to the semiconductor substrate, forming a blocking layer in the semiconductor substrate of both sides of the blocking side wall, and the top of the blocking layer is not higher than a bottom of a source region and a drain region formed in following steps; forming a grid structure on the epitaxial layer surface above the spacing layer; and taking the grid structure as a mask and carrying out a second ion implantation to the substrate formed with the epitaxial layer to form the source region and the drain region, and the source region and the drain region are in the epitaxial layer of both sides of the blocking side wall. The making method provided in the invention ameliorates short channel effect, reduces junction capacitance and junction current between the source region and the substrate and improves transistor performance.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a transistor and a manufacturing method thereof. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing. They are widely used in various integrated circuits. According to the main carrier and the type of doping during manufacturing, they are divided into NMOS and PMOS transistors. [0003] The prior art provides a method for manufacturing a transistor. Please refer to Figure 1 to Figure 3 , is a schematic cross-sectional structure diagram of a fabrication method of a transistor in the prior art. [0004] Please refer to figure 1 A semiconductor substrate 01 is provided, a gate oxide layer 02 and a gate 03 are formed on the semiconductor substrate 01, and the gate oxide layer 02 and the gate 03 form a gate structure. [0005] Next, please refer to figure 2 A lightly doped region 04 is formed in the se...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/335H01L29/78
Inventor 赵猛三重野文健
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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