Through silicon via (TSV) structure and manufacturing method thereof

Abstract

The invention relates to a TSV structure and a manufacturing method thereof, which include forming a window in a former medium layer and a semiconductor substrate, and forming a second blocking layer in the window before forming a plurality of interlayer medium layers; forming a through hole after forming the plurality of the interlayer medium layers, wherein the hole diameter of the through hole is smaller than that of the window after the second blocking layer is formed, accordingly, surplus initial filling medium layer forms a filling medium layer between the through hole and the window after the second blocking layer is formed; forming a first blocking layer and through hole metal in the through hole afterwards, so that a three layer isolating structure comprising the first blocking layer, the filling medium layer and the second blocking layer is formed between the through hole and the semiconductor substrate. The continuity of the isolating structure is improved, the problem of the degradation of semiconductor devices caused by the fact that conductive materials of the through hole metal diffuse into the semiconductor substrate is further effectively solved, and the reliability of semiconductor devices is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a through silicon via structure (through silicon via, TSV) for a three-bit stacked integrated circuit and a manufacturing method thereof. Background technique [0002] Since the advent of semiconductor technology, the integration of various electronic components has been continuously improved, and the entire semiconductor industry has experienced continuous and rapid development. So far, the increase in integration has mainly come from the reduction of the minimum feature size, enabling more components to be integrated into a given area. This integration is two-dimensional (2D), and dramatic improvements in lithography have played an important role in the fabrication of 2D integrated circuits, but there are physical limits to the density that can be achieved in two dimensions. [0003] To further increase circuit density, three-d...

AI Technical Summary

Problems solved by technology

The main challenge of 3D vertical stacking to form 3D interconnection lies in the fabrication of Through Silicon Via (TSV)

The barrier layer is usually completed by a physical vapor deposition (PVD) process. The typical PVD process has a small thickness and poor continuity along the sidewall at the bottom of the via, and because the TSV has a much larger aspect ratio than the existing process conditions Compared with that, the barrier layer forms a poor interface continuity. This poor continuity will cause the subsequent conductive material to diffuse into the substrate, causing degradation of device performance and reliability problems.

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