Storage and forming method thereof

Abstract

The invention relates to a storage and a forming method thereof. The storage comprises a semiconductor substrate, a first well region, a second well region, a first gate dielectric layer, a first grid electrode, first source / drain regions, a second gate dielectric layer, a second grid electrode, second source / drain regions, an interlayer dielectric layer and a metal layer, wherein the first well region is positioned in the semiconductor substrate; the second well region is isolated from the first well region; the first grate dielectric layer is positioned on the surface of the first well region; the first grid electrode is positioned on the surface of the first grate dielectric layer; the first source / drain regions are positioned at both sides of the first grate dielectric layer and the first grid electrode; the second grate dielectric layer is positioned on the surface of the second well region; the second grid electrode is positioned on the surface of the second grate dielectric layer; the second source / drain regions are positioned at both sides of the second grate dielectric layer and the second grid electrode; the first grid electrode is electrically connected with the second grid electrode by a grid electrode connecting layer positioned between the first grid electrode and the second grid electrode; the grid electrode connecting layer is electrically isolated from the surface of the semiconductor substrate by a first insulating layer; the interlayer dielectric layer is positioned on the surface of the first grid electrode; the metal layer is positioned on the surface of the interlayer dielectric layer; and the metal layer is electrically connected with the first well region by a first conductive plug positioned on the surface of the first well region. The performance of the storage is improved.

Description

Technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a memory and a method of forming the same. Background technique [0002] Electrically multi-erasable programmable memory (multiple time program, MTP) is a relatively common non-volatile memory, and because the electrical multi-erasable programmable memory has a simple manufacturing process and low cost, it has A wide range of applications, such as setting in embedded systems, PCs and peripherals, telecommunication switches, cellular phones, network interconnection and other equipment, used to store voice, image or data and other information. [0003] Please refer to Figure 1 to Figure 4 ,among them figure 1 It is a schematic diagram of the top view structure of the existing multiple erasable programmable memory, figure 2 for figure 1 The cross-sectional structure diagram in the AA' direction, image 3 for figure 1 The sectional structure drawing in the di...

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Problems solved by technology

[0008] However, the voltage coupling coefficient of the existing erasable and writable programmable memory is still relatively high, and a high operating voltage needs to be applied to the memory, so the energy consumption of the erasable and writable programmable memory is large and the performance is low. Low

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