Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A Fault-Tolerant Routing Method for On-Chip Internetwork Based on Channel Dependency Graph

An on-chip interconnection network and dependency graph technology, applied in data exchange networks, transmission systems, digital transmission systems, etc., can solve problems such as inability to fully play the role of faulty router components and waste of system resources, and achieve good scalability. performance and flexibility, low latency, and improved resource utilization

Inactive Publication Date: 2015-08-05
XI AN JIAOTONG UNIV
View PDF2 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Simple calibration of the router is completely invalid, and the role of the non-faulty components in some faulty routers cannot be fully utilized, which will cause a waste of system resources

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A Fault-Tolerant Routing Method for On-Chip Internetwork Based on Channel Dependency Graph
  • A Fault-Tolerant Routing Method for On-Chip Internetwork Based on Channel Dependency Graph
  • A Fault-Tolerant Routing Method for On-Chip Internetwork Based on Channel Dependency Graph

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0031] The present invention is described in detail below in conjunction with accompanying drawing.

[0032] A fault-tolerant routing method for on-chip Internet based on channel dependency graph, refer to figure 1 , including the following steps:

[0033] Step 1. First analyze the communication characteristics of the application modules, analyze whether there are communication requirements between the application modules, and generate a bipartite graph according to whether there are communication requirements between the application modules. Refer to image 3 The application modules in the bipartite graph are listed on both sides of the source node and the target node, and the solid line indicates that there is a communication requirement between the corresponding application modules; and the corresponding application module communication relationship matrix application traffic matrix, referred to as ATM, is generated by the ATM The corresponding bipartite graph of the comm...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to an on-chip internet fault-tolerance routing method based on channel dependency graphs, which comprises the steps of: firstly carrying out analysis on the communication characteristics of an application program, building a communication relation bipartite graph of an application program module, generating an application traffic matrix ATM, simultaneously generating a channel dependency directed graph CDG under the faultless condition, generating a faulty channel dependency directed graph FCDG under the fault condition by rough and fine granulation fault detection, and finally generating a corresponding acyclic fault channel dependency directed graph AFCDG and a corresponding flow consistency matrix FCM by applying a turning model; and secondly, carrying out matrix analysis on the ATM and FCM, selecting communicated AFCDG with single VC (virtual channel) or multiple VCs, setting the VC sequence, and finally obtaining an optimal load balancing routing plan by comparison. According to the method, the available resources are utilized to the greatest extent by a rough and fine granulation fault detection method, and the purposes of deadlock avoidance and load balancing are realized by constructing weighted acyclic fault channel dependency directed digraph AFCDG based on single VC or multiple VCs.

Description

technical field [0001] The invention relates to the technical field of reliability calculation, in particular to an on-chip interconnect network fault-tolerant routing method based on a channel dependency graph. Background technique [0002] With the continuous improvement of chip integration and the growing demand for complex calculations, computing systems are gradually developing from single-core to multi-core. In order to solve the complex problems of multi-core communication, Network-on-Chip (NoC) provides a solution with high performance, high scalability and high reliability, and has become the core technology of multi-core systems. [0003] The adoption of advanced semiconductor manufacturing technology and the surge in the number of integrated transistors on a single chip have greatly increased the probability of system failure, so the reliability of the system has become more and more important, that is, how to ensure the normal operation of the system in the prese...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/705H04L12/721H04L12/803H04L12/771H04L45/18H04L45/60
Inventor 任鹏举葛晨阳孟庆欣王全响杨挺刘卜郑南宁
Owner XI AN JIAOTONG UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com