Voltage buffer circuit and low dropout regulator (LDO) integrated with voltage buffer circuit

A voltage buffer and circuit technology, applied in instruments, regulating electrical variables, control/regulating systems, etc., can solve problems such as complex circuit structures, and achieve the effects of improving transient response, reducing costs, and reducing up-shooting peaks

Inactive Publication Date: 2012-11-14
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The purpose of the present invention is to solve the problem of complex circuit structure caused by the existing LDO to maxi

Method used

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  • Voltage buffer circuit and low dropout regulator (LDO) integrated with voltage buffer circuit
  • Voltage buffer circuit and low dropout regulator (LDO) integrated with voltage buffer circuit
  • Voltage buffer circuit and low dropout regulator (LDO) integrated with voltage buffer circuit

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Embodiment Construction

[0026] The present invention will be further theoretically analyzed below in conjunction with the accompanying drawings and specific embodiments.

[0027] The voltage buffer circuit proposed by the present invention is essentially a push-pull output super source follower circuit (Super Class AB Source Follower Circuit, SSFC), figure 2 An implementation form is given, including: three PMOS transistors MP BUF , MPB BUF , MP AB , two NMOS tubes MN AB , MNB BUF , two resistors R C , R BUF , and a capacitor C C . MP BUF The gate of the EA op amp is connected to the output signal V EA , drain and resistor R BUF Connected at one end, R BUF Connect the other end to ground potential, MP BUF The source of the buffer output is connected to the gate V of the pass transistor GMP . MN AB The gate and MP BUF The drain is connected, and the drain is connected to the MP BUF The source is connected, MN AB The source is connected to ground potential, MN AB with MP BUF Consti...

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Abstract

The invention discloses a voltage buffer circuit and a low dropout regulator (LDO) integrated with the voltage buffer circuit. The buffer circuit comprises a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first resistor unit, a second resistor unit, a capacitor element and a current source. The LDO of the voltage buffer circuit is integrated, the circuit stability is ensured at high-power tube gate parasitic poles, the current pull-down capacity of the power tube gate is improved, and the undershoot peak from light load to heavy load is reduced; due to the action of an RC high-pass coupling circuit in the buffer circuit, when the operating frequency of the circuit is near the filter cut-off frequency, the charging current of the power tube gate is increased, the overshoot peak from heavy load to light load is reduced, push-pull output is formed under the condition that the quiescent dissipation is not obviously increased, and the transient response of the LDO circuit is improved; and meanwhile, the LDO integrated with the voltage buffer circuit is simple in structure, and the chip area is saved.

Description

technical field [0001] The invention belongs to the technical field of power supply management, and in particular relates to the design of a low dropout linear regulator (Low Dropout Regulator, LDO). Background technique [0002] LDO has the advantages of low cost, low output noise, simple circuit structure, and small chip area, and has become an important circuit in power management chips. The essence of LDO is to use the stable voltage generated by the bandgap reference and the negative feedback control loop to obtain an output voltage that basically does not change with the environment. LDOs can convert the decaying battery voltage into a stable and accurate voltage with low noise to meet the needs of noise-sensitive analog modules and radio frequency modules in portable equipment. The transient response of the LDO is mainly determined by the loop bandwidth and the voltage slew rate of the power tube gate. [0003] In the design of LDO, the output transient response is ...

Claims

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Application Information

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IPC IPC(8): G05F1/56
Inventor 明鑫谭林潘福跃张竹贤黄建刚王鑫张晓敏段茂平王卓周泽坤张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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