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Manufacture method of depletion mode metal-oxide-semiconductor field effect transistor (MOSFET)

A manufacturing method and depletion-type technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as inability to manufacture high-quality depletion-type MOSFETs and inaccurate channel depth control

Inactive Publication Date: 2012-11-14
HANGZHOU SILAN INTEGRATED CIRCUIT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional depletion-mode MOSFET manufacturing method is not accurate enough to control the position and depth of the channel, and the ion implantation of the oxide layer will also cause disadvantages to other regions (such as the source region and the drain region). effect, making it impossible to manufacture high-quality depletion-mode MOSFETs

Method used

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  • Manufacture method of depletion mode metal-oxide-semiconductor field effect transistor (MOSFET)
  • Manufacture method of depletion mode metal-oxide-semiconductor field effect transistor (MOSFET)
  • Manufacture method of depletion mode metal-oxide-semiconductor field effect transistor (MOSFET)

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Embodiment Construction

[0026] The core idea of ​​the present invention is to use the mask layer to perform ion implantation to realize the channel of the depletion MOSFET. By using the mask layer, the position and structure of the channel can be precisely controlled, and the channel can be precisely controlled by adjusting the conditions of ion implantation. parameters such as depth and doping concentration. Precise trench structure, location, and depth enable high-performance depletion-mode MOSFETs.

[0027] In order to make the purpose, technical solution and advantages of the present invention more clear, the following will be further described in detail in conjunction with the accompanying drawings.

[0028] Such as Figure 7 As shown, the depletion MOSFET in one embodiment of the present invention includes: an N-type substrate 101; an N-type epitaxial layer 102 formed on one side of the substrate 101; a P-type epitaxial layer 102 formed in the N-type epitaxial layer 102 Doped deep well 105; N...

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Abstract

The invention discloses a manufacture method of a depletion mode metal-oxide-semiconductor field effect transistor (MOSFET). The manufacture method includes providing a first mingling type mingled substrate, forming a first mingling type epitaxial layer on one face of the substrate, forming a first mask layer on the epitaxial layer, conducting first ion injection with the first mask layer as a mask, forming a second mingling type trap in the epitaxial layer, removing the first mask layer, conducting first annealing, forming a second mask layer on the epitaxial layer and the trap, conducting second ion injection with the second mask layer as a mask and forming a first mingling type ion injection channel in the middle of the trap. The channel of the depletion mode MOSFET is formed by adopting ion injection of the mask layer, and high performance can be ensured by means of accurate structure, position and depth of the channel.

Description

technical field [0001] The invention belongs to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a depletion MOSFET. Background technique [0002] MOSFETs are divided into enhancement-mode MOSFETs and depletion-mode MOSFETs. For the depletion-mode MOSFET, because a large number of ions are doped in the oxide layer of the source and drain electrodes, even when the gate voltage VGS=0, under the action of the doped ions in the oxide layer, the surface layer of the substrate will induce The bottom doping type is opposite and the majority carriers form an inversion layer, that is, there is a channel between the source and the drain. As long as a forward voltage is applied between the source and the drain, the drain current can be generated; when the gate voltage VGS is applied, Most carriers will flow out of the channel, the inversion layer becomes narrower and the channel resistance increases. When the gate voltage VGS increases to...

Claims

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Application Information

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IPC IPC(8): H01L21/336
Inventor 赵金波王维建曹俊
Owner HANGZHOU SILAN INTEGRATED CIRCUIT
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