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Outer-pin-free flat semiconductor package structure adopting elastic device

A technology of elastic device and packaging structure, which is applied in the direction of semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve the problems of unsatisfactory heat dissipation effect, signal transmission speed of short signal transmission path, etc., and achieve good heat dissipation effect, Improve the yield rate and suit the effect of integration

Active Publication Date: 2015-01-07
GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, the quad flat no-lead package has a shorter signal transmission path and faster signal transmission speed, but the heat sink of the quad flat no-lead package structure can only be arranged on the surface of the package structure, therefore, either no heat dissipation device is provided , or a heat sink is provided on one side. With the miniaturization and increase in complexity of the semiconductor package structure, the heat dissipation effect of the above-mentioned heat dissipation structure cannot meet the requirements of the existing semiconductor package structure.

Method used

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  • Outer-pin-free flat semiconductor package structure adopting elastic device
  • Outer-pin-free flat semiconductor package structure adopting elastic device
  • Outer-pin-free flat semiconductor package structure adopting elastic device

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Embodiment Construction

[0038] The present invention will be further described in conjunction with the following examples.

[0039] A semiconductor flat packaging structure without outer pins using elastic devices according to the present invention, such as Figure 1 to Figure 4 As shown, lead frame 100 includes at least one die holder 110 and a plurality of inner leads 120 positioned around die holder 110, inner leads 120 having inner and outer surfaces. The chip 300 is located on the upper surface of the chip holder 110 and is electrically connected to the inner pins 120 . The chip 300 is connected to the inner pin 120 through the connection sheet 700 , one section of the connection sheet 700 is fixed on the upper surface of the chip 300 , and the other section is fixed on the inner surface of the inner lead 120 . The elastic cooling plate 400 is fixed on the upper surface of the connecting sheet 700 . Colloid 500 , the colloid 500 covers the lead frame 100 , the chip 300 , and the elastic heat d...

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Abstract

The invention discloses an outer-pin-free flat semiconductor package structure adopting an elastic device. The outer-pin-free flat semiconductor package structure comprises a lead frame, a chip, a connection sheet, an elastic heat dissipation plate and colloid, wherein the colloid covers the lead frame, the chip and the elastic heat dissipation plate; and the bottom surface of a chip seat, the outer surfaces of inner pins and the top surface of the elastic heat dissipation plate are exposed from the colloid. With the adoption of the elastic heat dissipation plate, elastic semiconductor package is realized; glue is prevented from overflowing from the top of the elastic heat dissipation plate, and the chip cannot be crushed by pressure produced by die assembly of an upper die and a lower die during package; the chip is effectively protected, and the yield of the package structure is improved; the chip seat can be used as a chip carrier and a bottom heat dissipation plate; with the elastic heat dissipation plate and the chip seat at the bottom, an effect of dissipating heat from two surfaces is achieved; the heat dissipation effect of the package structure is relatively good; and the outer-pin-free flat semiconductor package structure is suitable for integration and relatively high in minimization.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a flat semiconductor packaging structure without external leads using an elastic device. Background technique [0002] Semiconductor packaging refers to the process of processing the tested wafers according to the product model and functional requirements to obtain independent chips. The packaging process is: the wafer is cut into small chips after the dicing process, and then the cut chips are glued to the corresponding small island of the substrate frame, and then ultra-fine metal wires or conductive resin are used to Connect the bonding pads of the chip to the corresponding pins of the substrate to form the required circuit; then package and protect the independent chip with a plastic case. [0003] With the rapid development of microelectronics technology and the increase in the complexity of integrated circuits, semiconductor packaging structures are require...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/373
CPCH01L2924/00014H01L2224/40245H01L2224/37099
Inventor 徐振杰陶少勇何錦文曹周
Owner GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD