Preparation method for silicon-based nanometer array patterned substrate and silicon-based epitaxial layer

A patterned substrate and silicon nano-array technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of high cost and complicated process, and achieve low cost, simple preparation process, and high crystal quality Effect

Active Publication Date: 2012-12-26
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a silicon-based nano-array patterned

Method used

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  • Preparation method for silicon-based nanometer array patterned substrate and silicon-based epitaxial layer
  • Preparation method for silicon-based nanometer array patterned substrate and silicon-based epitaxial layer
  • Preparation method for silicon-based nanometer array patterned substrate and silicon-based epitaxial layer

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Embodiment 1

[0034] As shown in the figure, this embodiment provides a method for preparing a silicon-based nanoarray patterned substrate, including the following steps:

[0035] First, if figure 1 As shown, in step 1, a silicon substrate 10 is provided, and the crystal plane of the silicon substrate 10 is (100). Since the crystal orientation of the film must best match the crystal orientation of the surface of the silicon substrate 10 to be epitaxial, in the subsequent When Ge is epitaxially grown on the (100) crystal plane of the silicon substrate 10, it is more conducive to releasing the tensile stress, but it is not limited thereto, and other crystal planes of silicon can also be used in other embodiments; then the silicon substrate 10 is placed into the predetermined concentration of AgNO 3 The silicon substrate 10 with the silicon nano-array 100 is formed by chemical catalytic etching in a mixed solution of HF and HF. During etching, a certain amount of ammonium fluoride can be adde...

Embodiment 2

[0044] As shown in the figure, this embodiment provides a method for preparing a silicon-based epitaxial layer, including the following steps:

[0045] Step 1: Using the method described in Embodiment 1 of the present invention to prepare a silicon-based nanoarray patterned substrate, the specific process will not be described in detail in this embodiment, and the specific process diagram refers to Embodiment 1 figure 1 ,, Figure 2a-2b ,as well as Figure 3a~3b .

[0046] Step 2: growing an epitaxial layer 12 on the silicon-based nano-array patterned substrate by using a selective epitaxy process. The selective epitaxy process is a common method used by those skilled in the art and will not be repeated here. In this implementation, the epitaxial layer 12 is temporarily selected as a Ge layer, but it is not limited thereto. In other embodiments, the parameters of the preparation process of the silicon-based nanoarray patterned substrate and the parameters of the epitaxial pr...

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Abstract

The invention provides a preparation method for a silicon-based nanometer array patterned substrate and a silicon-based epitaxial layer. The preparation method comprises the following steps of: preparing the silicon-based nanometer array patterned substrate by using a chemical catalytic corrosion method; and then epitaxially arranging a Ge or III-V compound on the silicon-based nanometer array patterned substrate, so that a Ge or III-V compound epitaxial layer with low defect density and high crystalline quality can be obtained. In addition, the preparation method provided by the invention has the advantages of simple preparation process and low cost and is beneficial for popularization and application.

Description

technical field [0001] The invention relates to a method for preparing a patterned substrate, in particular to a method for preparing a silicon-based nano-array patterned substrate and a silicon-based epitaxial layer. Background technique [0002] As the size of semiconductor devices shrinks, traditional bulk silicon materials are approaching their physical limits. Ge and III-V materials have attracted extensive attention due to their high mobility. However, Ge and III-V bulk materials are expensive and small in size , and not compatible with silicon-based processes. During epitaxy on a silicon substrate, due to the mismatch between the lattice constants or thermal expansion coefficients of germanium and III-V materials and silicon materials, the defect density of germanium and III-V materials prepared by epitaxy is high, and the epitaxial thickness is thick, resulting in high cost. In the case of low device performance was obtained. [0003] In order to suppress the gener...

Claims

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Application Information

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IPC IPC(8): H01L21/306H01L21/20
Inventor 张苗母志强薛忠营陈达狄增峰王曦
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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