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Three-dimensional packaging device for photonic integrated chip matching circuit

A technology of photonic integration and matching circuits, applied in circuits, optical multiplexing systems, optics, etc., can solve the problems of increasing circuit design dimensions and limited matching circuit size, and achieve impedance matching, enhanced heat dissipation, and improved The effect of modulation efficiency

Active Publication Date: 2014-11-05
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of this, the main purpose of the present invention is to provide a three-dimensional packaging device for photonic integrated chip matching circuits, to overcome the problem of limited matching circuit size caused by the limitation of array chip spacing when packaging photonic integrated chip arrays, and to break through the microwave circuit. The traditional design is only limited by the two-dimensional plane, which increases the dimension of the circuit design and reserves space for the design of microwave circuits

Method used

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  • Three-dimensional packaging device for photonic integrated chip matching circuit
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  • Three-dimensional packaging device for photonic integrated chip matching circuit

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Embodiment Construction

[0032] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0033] Such as figure 1 as shown, figure 1 It is a structural schematic diagram of a three-dimensional packaging device for a photonic integrated chip matching circuit provided by the present invention. The device includes: a first carrier substrate 1; a first microwave transmission line array 2 evaporated on the first carrier substrate 1 The surface is used to provide bias voltage and high-frequency modulation signal to the photonic integrated chip; a second carrier substrate 3 is perpendicular to or at a certain angle with the first carrier substrate 1 to form a three-dimensional structure; a second microwave transmission line An array 4 is vapor-deposited on the lower surface of the second carrier substrate 3, and is ...

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Abstract

A 3D package device of a photonic integrated chip matching circuit, comprising: a first carrier substrate; a first microwave transmission line array formed by evaporation on the top surface of the first carrier substrate to provide bias voltages and high-frequency modulation signals to the photonic integrated chip; a second carrier substrate formed perpendicularly to the first carrier substrate or to have a certain angle with respect to the first carrier substrate, so as to constitute a 3D structure; a second microwave transmission line array formed by evaporation on the bottom surface of the second carrier substrate to match electrodes of the first microwave transmission line array, the second microwave transmission line array being soldered or sintered with the electrodes of the first microwave transmission line array; an electrode array formed by evaporation on a side surface or two opposite side surfaces of the second carrier substrate; and a microwave circuit.

Description

technical field [0001] The invention belongs to the field of optoelectronic devices, in particular to a three-dimensional packaging device for photonic integrated chip matching circuits. Background technique [0002] At present, optical network equipment constructed by discrete optoelectronic devices is difficult to adapt to the rapidly developing optical fiber communication network. Photonic integrated chip (PIC) is a technology that must be relied on to realize large-capacity and low-power optical networks. In order to effectively load the external microwave signal to the photonic integrated chip, the transitional heat sink is required to have an impedance matching microwave circuit with high efficiency, low reflection and low loss. [0003] Significantly different from discrete devices, ultra-high integration reduces the scale of integrated devices to the micro-nano level, which puts forward stricter requirements for the development and packaging of devices. The circuit ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/58H01L23/66H01L23/367
CPCH01Q13/206H01L23/58H01L2224/48091H01P11/003G02B6/00H04J14/00H01P1/36H01L2224/45144H01L23/66G02F1/0121H01L2924/00014H01L2924/00
Inventor 祝宁华王佳胜刘建国刘宇
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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