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Transient voltage suppressor and application thereof

A technology of transient voltage suppression and injection area, which is applied in the direction of electric solid-state devices, circuits, electrical components, etc., can solve problems such as difficult ESD protection, high trigger voltage, and small application range, and achieve good ESD clamping characteristics, conduction Small on-resistance and strong ESD conduction capability

Inactive Publication Date: 2013-01-02
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Among them, the trigger voltage of the diode is too low, and the application range is small; the protection ability of the SCR is very good, but its maintenance voltage is low, the trigger voltage is high, and its characteristic curve has a large hysteresis phenomenon, so it is difficult to be directly used for ESD. protection
[0005] GGMOS has a lower trigger voltage and higher sustain voltage, but its protection ability is poor; its structure and equivalent circuit are shown in Figure 2: the GGMOS device includes a P substrate 101, two N+ active injection regions 102~ 103, a P+ active injection region 104, a gate 105, a field oxygen isolation 106

Method used

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  • Transient voltage suppressor and application thereof
  • Transient voltage suppressor and application thereof
  • Transient voltage suppressor and application thereof

Examples

Experimental program
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Embodiment 1

[0035] Such as image 3 and Figure 5 As shown, a transient voltage suppressor includes a P substrate 10;

[0036] N well 20, first N+ active injection region 31 and first P+ active injection region 41 are embedded on P substrate 10; second N+ active injection region 32 and second P+ active injection region 41 are embedded on N well 20. a source implantation region 42; a third N+ active implantation region 33 is embedded at the junction of the P substrate 10 and the N well 20;

[0037] The second P+ active injection region 42 is adjacent to the second N+ active injection region 32 and the third N+ active injection region 33; the first N+ active injection region 31 is adjacent to the third N+ active injection region 33 and the first The P+ active injection region 41 is adjacent to the left and right;

[0038] A gate region 5 is provided on the P substrate 10 between the first N+ active implant region 31 and the third N+ active implant region 33, and the first N+ active impla...

Embodiment 2

[0051] Such as Figure 7 As shown, a finger-type transient voltage suppressor includes two transient voltage suppressors as described in Embodiment 1; two transient voltage suppressors share a P substrate, and two transient voltage suppressors The anodes are connected together as the anode of the finger-type transient voltage suppressor, and the cathodes of the two transient voltage suppressors are connected together as the cathode of the finger-type transient voltage suppressor.

[0052] The finger-type transient voltage suppressor can further enhance the ESD current conduction capability of the device; it is manufactured under the 0.35um standard CMOS process, through Figure 8 It can be seen from the measured experimental data that the ESD current conduction capability of two interfinger transient voltage suppressors is stronger than that of a single transient voltage suppressor, the trigger voltage and sustain voltage of the device remain basically unchanged, and the curre...

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Abstract

The invention discloses a transient voltage suppressor, which comprises a P substrate embedded with an N well, a first N+ active injection area and a first P+ active injection area. A second N+ active injection area and a second P+ active injection area are embedded into the N well. A third N+ active injection area is embedded at a junction of the P substrate and the N well. The P substrate between the first N+ active injection area and the third N+ active injection area is provided with a grid region. The second N+ active injection area is led out through a metal line to be used as an anode of the transient voltage suppressor, and the grid region is connected with the first N+ active injection area and the first P+ active injection area and led out through the metal line to be used as a cathode of the transient voltage suppressor. The transient voltage suppressor provided by the invention has relatively low trigger voltage and relatively high maintaining voltage, is small in hysteresis and strong in ESD (Electro-Static Discharge) conductive capacity, and has stronger ESD protective capacity.

Description

technical field [0001] The invention belongs to the technical field of electrostatic protection of off-chip integrated circuits, and in particular relates to a transient voltage suppressor and its application. Background technique [0002] With the development of the semiconductor integrated circuit industry, the ESD (Electrostatic Discharge, electrostatic discharge) problem has always been a troublesome problem in this field. Doing a good job of electrostatic protection for integrated circuits is extremely important to the reliability of an electronic system. Nowadays, electronic devices tend to be miniaturized, high-density, and multi-functional. Especially, applications such as fashion consumer electronics and portable products that have strict requirements on the motherboard area are easily affected by electrostatic discharge. Static electricity exists all the time and everywhere. In the 1960s, with the emergence of MOS devices that are very sensitive to static electric...

Claims

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Application Information

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IPC IPC(8): H01L27/02
Inventor 董树荣曾杰吴健钟雷戴一思
Owner ZHEJIANG UNIV
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