Gain embedded dynamic random access memory (eDRAM) unit structure

Abstract

The invention belongs to the technical field of a memory and discloses an improved gain embedded dynamic random access memory (eDRAM) component structure. The gain eDRAM unit comprises a reading metal oxide semiconductor (MOS) transistor, a writing MOS transistor, a writing line, a writing position line, a reading line and a reading position line, wherein the grid of the reading MOS transistor and the drain of the writing MOS transistor are connected through a metal wire to form a memory node; and the writing MOS transistor and the reading MOS transistor respectively have a grid medium. The gain eDRAM unit is characterized in that the writing MOS transistor and the reading MOS transistor have slot channels; the grid mediums of the writing MOS transistor and the reading MOS transistor are arranged in a silicon substrate slot; and the grids are of convex cylindrical structures which are protruded downwards. According to the gain eDRAM unit, the data holding property of the component is remarkably improved.

Description

technical field [0001] The invention belongs to the technical field of memory and provides an improved gain-type eDRAM device structure. Background technique [0002] Such as figure 1 Shown is Intel's 2T Gain Cell eDRAM unit. The Gain Cell eDRAM 100 includes a write MOS transistor 101, a read MOS transistor 102, a write word line (Write Word Line, WWL) 105, a read word line (Read Word Line, RWL) 106, and a write bit line (Write Bit Line, WBL) 107 , a read bit line (Read Bit Line, RBL) 108 and an equivalent parasitic capacitance 104 (the equivalent parasitic capacitance does not exist as an independent device, and is only schematically shown separately in the figure). Wherein, the drain region of the write MOS transistor 101 is connected to the gate of the read MOS transistor 102, the MN point 103 is a storage node, one end of the equivalent parasitic capacitance 104 is connected to 103, and the other end is grounded, therefore, the potential level of the MN point can be co...

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Problems solved by technology

The problem with this unit is that the leakage is serious, and the data retention time is too short. The data retention time is only about 10us when using the standard logic process under 65nm, so the refresh frequency is very high, and the power consumption increases.

[0009] In order to reduce the subthreshold leakage 110, the doping concentration of the substrate needs to be increased, but larger substrate doping increases the electric field strength near the storage node 104, and the PN junction leakage 111 increases accordingly, becoming the main component of the leakage current. The high electric field near 104 may also intensify the tunneling effect, causing additional tunneling current, so the total leakage current does not decrease, but increases;

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