Test device and manufacturing method thereof, semiconductor device and manufacturing method thereof

Abstract

The invention discloses a test device, a test device manufacturing method, a semiconductor device and a semiconductor device manufacturing method. The test device comprises a semiconductor substrate, a dielectric layer positioned on the semiconductor substrate and an electrical connecting line positioned on the dielectric layer, wherein the dielectric layer is made from silicon oxide formed by adopting TEOS (tetraethyl orthosilicate) as a reaction source; the dielectric layer comprises metal plugs and dummy contacts; the dummy contacts can be made of tungsten; the ratio of the upper surface area of the dummy contacts to the upper surface area of the whole dielectric layer is greater than or equal to 20 percent; and the electrical connecting line can be made of copper, aluminum or copper aluminum alloy. The semiconductor device comprises a plurality of dies and cutting channels positioned between the dies, and the cutting channels comprise the test devices. According to the invention, the adhesive force between the electrical connecting line and the dielectric layer of the test device can be increased and finally the stable performance of the semiconductor device can be ensured.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a testing device and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof. Background technique [0002] In the field of semiconductor manufacturing, multiple chips (Die) with the same structure are usually manufactured simultaneously on a semiconductor wafer, and the area between adjacent chips is a dicing line. In order to ensure the reliability of semiconductor devices, multiple test devices are usually fabricated in the dicing line for testing some key parameters (such as: RS resistance value). Different semiconductor devices may need to obtain different test parameters, and different test parameters may require different test devices. When the chip manufacturing process is completed and the test devices in the dicing lanes meet the requirements, the wafer can be cut along the predetermined dicing lanes to form discrete chips, and ...

AI Technical Summary

Problems solved by technology

[0009] However, after dicing along the dicing line including the above-mentioned test devices, the electrical properties of the corresponding chips changed greatly, resulting in the scrapping of the chips in the entire wafer

Images