Duty ratio adjusting circuit

Abstract

The invention provides a duty ratio adjusting circuit which is used for adjusting the duty ratio of a first clock signal to acquire a third clock signal. The duty ratio adjusting circuit comprises a pulse width adjusting unit, a shaping unit, an inverse phase unit and a control signal generating unit, wherein the pulse width adjusting unit inputs a second clock signal and outputs the third clock signal; the inverse phase unit inputs the third clock signal and outputs a fourth clock signal; the third clock signal and the fourth clock signal have opposite phase position; and the control signal generating unit inputs the third clock signal and the fourth clock signal and outputs a control signal. The duty ratio adjusting circuit is simple in structure and can stably output the clock signal with the expected duty ratio.

Description

Technical field [0001] The present invention relates to the technical field of integrated circuits, in particular to a duty cycle adjustment circuit which is not affected by manufacturing process, voltage and temperature parameters. Background technique [0002] With the continuous development of integrated circuit technology, the working speed of the chip continues to increase, and the increase in working speed means more stringent timing accuracy. Therefore, the requirements for system clock performance are also constantly improving. The duty cycle of the clock is a relatively important performance index in the clock performance. Duty Cycle usually refers to the ratio of the duration of a positive pulse to the pulse period in a series of ideal pulse cycle sequences (such as a square wave). For example, a duty cycle of 50% means that the width of the high-level clock cycle is equal to the width of the low-level clock cycle. For now, a 50% duty cycle is more beneficial to data ...

AI Technical Summary

Problems solved by technology

Therefore, the clock signal output by the RO depends to a large extent on factors such as process conditions, temperature, and the operating voltage of the RO, which will make the duty cycle of the final clock signal output by the RO less than 50%, resulting in the charge pump CPB The charging time and discharging time of capacitor C6 are not equal, so that the reference voltage V6 at the inverting input of the input amplifier is not the DC potential corresponding to the clock signal with a duty cycle of 50%.

[0009] In summary, using figure 1 In the duty cycle adjustment circuit shown, the adjusted clock signal often does not reach a 50% duty cycle, and the adjustment circuit is more complicated

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