Feature Size Shrinking Method

Abstract

The invention relates to the technical field of semiconductors and discloses a critical dimension shrink method. According to the invention, CO is adopted to replace the traditional fluorocarbon compounds and H-containing fluorocarbon gases, and serves as a high molecular polymer gas in the critical dimension shrink method to support plasma etching under low-frequency radio-frequency power, so as to effectively control the molecular chain length and plasma energy and density in the critical dimension shrink process. The method can control the molecular chain lengths of polymers resulting from plasma etching and avoid the formation of long molecular chain polymers during the plasma etching process. Besides, the plasma etching process of the critical dimension shrink method is carried out under a high pressure environment, to further improve the phenomenon of physical bombardment of polymer deposition during the etching process, so as to effectively prevent the formation of stripes and improve the line edge roughness of the etched structure resulting from critical dimension shrink. The critical dimension shrink method can further improve the process quality and ensure the effective and high-quality shrink of critical dimension.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to the feature dimension shrinkage technology after photolithography under the next-generation semiconductor process node. Background technique [0002] With the continuous development of integrated circuit technology, semiconductor process nodes have gradually entered the era of 65nm and 45nm, and are moving towards more advanced 22nm and 16nm. However, as semiconductor process nodes continue to advance, the requirements for critical dimension (CD) in semiconductor device fabrication front-end process (FEOL) and back-end process (BEOL) become more and more stringent. Among them, the feature size of devices in the 65nm process has begun to be much smaller than the size of mainstream lithography. In the process of semiconductor device preparation, more and more semiconductor structures with feature sizes smaller than 65nm, or even smaller than 45nm and 28nm have begun to appea...

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