C-to-RTL comprehensive method based on visual fields intact (VFI) optimization

Abstract

The invention relates to the technical field of the automation of hardware design, in particular to a C-to-RTL comprehensive method which is used for optimizing assembly line division, module parallelism and VFI distribution and orients to application specific integrated circuit (ASIC) hardware design. For hardware design, an assembly line and a parallel structure are two most effective means for improving the hardware performance; meanwhile, in the large-scale ASIC design, the design of VFI can greatly reduce the power consumption; and according to the C-to-RTL comprehensive method based on VFI optimization, the assembly line division, the module parallelism and the VFI distribution are optimized simultaneously during a C-to-RTL comprehensive process; and meanwhile, compared with a method which optimizes step by step through three optimization processes, the method ensures the global optimality. In such a manner, according to the C-to-RTL comprehensive method based on VFI optimization, the practicality and the scope of application of a C-to-RTL comprehensive technology are improved, and powerful technical support is provided for hardware design.

Description

technical field [0001] The invention relates to the technical field of hardware design automation, in particular to a C-to-RTL synthesis method for ASIC hardware design with pipeline division, module parallelism and VFI (Voltage-Frequency Islands, Voltage-Frequency Islands) allocation optimization. Background technique [0002] In the field of integrated circuits, ASIC (Application Specific Integrated Circui, Application Specific Integrated Circuit) is considered to be an integrated circuit designed for a special purpose. The characteristic of ASIC is that it is oriented to the needs of specific users. Compared with general-purpose integrated circuits, ASIC has the advantages of smaller size, lower power consumption, improved reliability, improved performance, enhanced confidentiality, and reduced cost when mass-produced. [0003] For ASIC hardware design, C-to-RTL synthesis is very advantageous; C-to-RTL synthesis refers to directly converting the C program at the algorithm...

AI Technical Summary

Problems solved by technology

[0004] However, there are still many unresolved problems in the existing C-to-RTL synthesis technology, for example: (1), when synthesizing large-scale C programs, the quality of the synthesis results is not ideal; (2), users cannot The performance (throughput rate, area and power consumption, etc.) is optimized and the constraints are given; (3), the optimization of power consumption at the system level is not ideal, especially in ASIC-oriented design; (4) ), the technology currently does not support VFI design

The root causes of these problems are mainly: the design and optimization of high-level or system-level hardware architecture has not been considered, and the C language cannot express the timing, parallelism, architecture, etc. in the hardware.

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