Manufacturing method for semiconductor device

A semiconductor and device technology, applied in the field of manufacturing semiconductor devices, can solve problems such as difficult to take into account both N-type transistors and P-type transistors, high threshold voltage, and lower threshold voltage of P-type transistors

Active Publication Date: 2013-05-08
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
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  • Application Information

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Problems solved by technology

However, since the covering layer under the N-type metal gate and the P-type metal gate is the same, if the work function of the covering layer is higher, the threshold voltage (Vt) of the P-type transistor will be reduced, and vice versa, the threshold voltage (Vt) of the N-type transistor will be reduced. threshold voltage, th

Method used

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  • Manufacturing method for semiconductor device
  • Manufacturing method for semiconductor device
  • Manufacturing method for semiconductor device

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Embodiment Construction

[0027] Next, the present invention will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0028] It should be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when...

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Abstract

The invention discloses a manufacturing method for a semiconductor device. The manufacturing method for the semiconductor device comprises: a) a semiconductor substrate is provided, wherein the semiconductor substrate comprises a P-type transistor area and an N-type transistor area, and a gate dielectric layer and a covering layer are sequentially formed on the semiconductor substrate; b) a photoresist layer which exposes the P-type transistor area is formed on the covering layer; c) nitrogen treatment process is carried out, and nitrogen is mixed in the gate dielectric layer and the covering layer of the P-type transistor area; d) the photoresist layer is removed. By the fact that the nitrogen-atoms are mixed in the gate dielectric layer and the covering layer of the P-type transistor area to replace oxygen atoms at the interface, effective work function value of the covering layer in the P-type transistor area is increased, threshold voltage of a P-type transistor is reduced, so that the covering layer can be matched with work function layers of the P-type transistor area and the N-type transistor area at the same time.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a semiconductor device. Background technique [0002] As the gate size shrinks to tens of nanometers, the thickness of the gate oxide layer drops below 3nm, causing problems such as excessive gate resistance, increased gate leakage, and depletion of the polysilicon gate. Therefore, people turn their attention to the metal gate technology again. The metal gate technology uses a metal with a lower resistance as the gate, and a material with a larger dielectric constant as the gate dielectric layer. [0003] The metal gate technology includes a gate-first process and a gate-last process. The Gate-first process refers to the formation of metal gates before performing drain / source region ion implantation and subsequent high-temperature annealing steps on the silicon wafer, while the Gate-last process is the opposite. Since the metal gate in the Gate...

Claims

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Application Information

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IPC IPC(8): H01L21/8238H01L21/28
Inventor 陈勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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