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Encapsulating method of advanced square flat pins-free and encapsulating structure thereof

A packaging method, square and flat technology, applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of small number of I/O, low integration, large packaging volume, etc., to achieve high input and output , good electrical performance and heat dissipation performance, and the effect of reducing the size of the package

Active Publication Date: 2013-05-15
美新半导体(天津)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the existing traditional QFN packaging method, such as the small number of I / O per unit area, low integration, and large packaging volume.

Method used

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  • Encapsulating method of advanced square flat pins-free and encapsulating structure thereof

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Embodiment Construction

[0024] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0025] In one embodiment of the packaging method of AQFN involved in the present invention, it comprises the following steps:

[0026] First, provide lead frames for wafers, chips, and copper substrates, where the size of the lead frame can be consistent with the size of the lead frame in the traditional QFN packaging method, so that the same set of plastic packaging molds can be used when changing the packaging method, reducing equipment molds input cost;

[0027] The lead frame is half-etched, and the front of the wafer forms cylindrical bump pins arranged in a normal distribution. The diameter of the pins is 0.23mm and the height is 0.08mm. On the pad, to prevent the plastic sealant from overflowing and covering the pad during subsequent plastic packaging;

[0028] Next, thin the wafer to 100um or other predetermined thickness that meets ...

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Abstract

The invention relates to an encapsulating method of an advanced square flat pins-free and an encapsulating structure of the advanced square flat pins-free. The encapsulating method includes the following steps: a wafer, a chip and a leading wire frame are provided. The leading wire frame is half etched. Pins arranged in a normality distribution mode are formed on the front side of the wafer. The thickness of the wafer is reduced to the preset thickness and the wafer is scrapped into pieces. The chip is placed in an island area of the leading wire frame. The chip is solidified, the leading wire frame with the chip placed is cleaned and the leading wire is bonded. The advanced square flat pins-free is plastic packaged by a plastic packaging machine in a plastic mode. An uncut dambar is formed through a half etching step between the pins and the pins in the leading wire frame and the uncut dambars are etched in a wet mode, thus the uncut dambars are disconnected and the pins are separated. The pins are cleaned and the pins are electroplated after that the pins are cleaned. The advanced square flat pins-free is labeled on the surface of a plastic package body. The leading wire frame is incised, thus a single body encapsulation product is formed. By means of the encapsulating method of advanced square flat pins-free and the encapsulating structure of the advanced square flat pins-free, an input / output (I / O) connecting way is improved, an I / O port in an unit encapsulating surface area is effectively improved, thus the integratable degree in the same encapsulating surface area is improved.

Description

technical field [0001] The invention relates to semiconductor packaging technology, in particular to an advanced square flat non-lead packaging method and its packaging structure. Background technique [0002] The development of today's electronic consumer products is changing with each passing day, showing that the functional integration is getting higher and higher, and the volume is getting smaller and smaller, especially the thickness of electronic products is shrinking. The market share exceeds that of ordinary mobile phones, especially Apple's iphone4 and Android-based smart phones. [0003] The existing traditional QFN package (QFN, short for Quad Flat No-lead, square flat no lead) uses a copper alloy frame for penetrating etching, and partially uses half-etching, and then performs chip loading, wire bonding, plastic packaging, A series of process steps such as cutting can only achieve two rows of staggered pins at most, resulting in a small number of input and outpu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/56H01L23/495H01L23/31
CPCH01L2924/0002H01L2924/00
Inventor 陈慧段志伟李晓燕
Owner 美新半导体(天津)有限公司
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