Superlattice nanowire field effect transistor and forming method thereof

Abstract

Provided are a superlattice nanowire field effect transistor and a forming method thereof. The forming method of the superlattice nanowire field effect transistor comprises the steps that a substrate is provided, a groove is formed in the substrate, at least two layers of overlapped nanowires and a gate electrode structure are arranged on the substrate, the nanowires are arranged in the groove in a suspended mode, a scheduled distance is arranged between the mutually overlapped nanowires, the gate electrode structure comprises a gate electrode and a gate medium layer located between the gate electrode and the nanowires, the gate electrode structure is located on the bottom of the groove and surrounds the at least two layers of overlapped nanowires, and the length of the nanowires is larger than the width of the gate electrode; side walls are formed on the periphery of the electrode gate structure; the nanowires stretching out of the side walls are removed; source electrodes and drain electrodes are formed on outer sides of the side walls by means of an epitaxial growth method. According to the technical scheme, the source electrodes and the drain electrodes are formed by means of the epitaxial growth method, ions needing doping can be doped in the source electrodes and the drain electrodes along with forming of the source electrodes and the drain electrodes, and the problem of uneven ion doping in the source electrodes and the drain electrodes caused by the fact that ions are poured into the source electrodes and the drain electrodes in the prior art is avoided.

Description

technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a superlattice nanowire field effect transistor (superlattice nanowire FET) and a method for forming the same. Background technique [0002] Integrated circuits have evolved from integrating dozens of devices on a single chip to integrating millions of devices. The performance and complexity of traditional integrated circuits have far exceeded initial expectations. To achieve increases in complexity and circuit density (the number of devices that can fit in a given chip area), the feature size of a device, also known as "geometry," has increased with each generation of integrated circuits. getting smaller. Increasing the density of integrated circuits can not only increase the complexity and performance of integrated circuits, but also reduce consumption for consumers. Based on the demand for high density, high speed and low power consumption of integrated circu...

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Problems solved by technology

[0013] The problem solved by the present invention is the problem of non-uniform distribution of ions in the source and drain electrodes of the method for forming superlattice nanowire field effect transistors in the prior art

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